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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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29217a4746
On the bare metal, enabling X2APIC mode requires interrupt remapping function which helps to deliver irq to cpu with 32-bit APIC ID. Hyper-V doesn't provide interrupt remapping function so far and Hyper-V MSI protocol already supports to deliver interrupt to the CPU whose virtual processor index is more than 255. IO-APIC interrupt still has 8-bit APIC ID limitation. This patch is to add Hyper-V stub IOMMU driver in order to enable X2APIC mode successfully in Hyper-V Linux guest. The driver returns X2APIC interrupt remapping capability when X2APIC mode is available. Otherwise, it creates a Hyper-V irq domain to limit IO-APIC interrupts' affinity and make sure cpus assigned with IO-APIC interrupt have 8-bit APIC ID. Define 24 IO-APIC remapping entries because Hyper-V only expose one single IO-APIC and one IO-APIC has 24 pins according IO-APIC spec( https://pdos.csail.mit.edu/6.828/2016/readings/ia32/ioapic.pdf). Reviewed-by: Michael Kelley <mikelley@microsoft.com> Signed-off-by: Lan Tianyu <Tianyu.Lan@microsoft.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
78 lines
2.2 KiB
C
78 lines
2.2 KiB
C
/*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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* Author: Joerg Roedel <jroedel@suse.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* This header file contains stuff that is shared between different interrupt
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* remapping drivers but with no need to be visible outside of the IOMMU layer.
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*/
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#ifndef __IRQ_REMAPPING_H
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#define __IRQ_REMAPPING_H
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#ifdef CONFIG_IRQ_REMAP
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struct irq_data;
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struct msi_msg;
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struct irq_domain;
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struct irq_alloc_info;
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extern int irq_remap_broken;
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extern int disable_sourceid_checking;
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extern int no_x2apic_optout;
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extern int irq_remapping_enabled;
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extern int disable_irq_post;
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struct irq_remap_ops {
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/* The supported capabilities */
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int capability;
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/* Initializes hardware and makes it ready for remapping interrupts */
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int (*prepare)(void);
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/* Enables the remapping hardware */
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int (*enable)(void);
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/* Disables the remapping hardware */
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void (*disable)(void);
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/* Reenables the remapping hardware */
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int (*reenable)(int);
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/* Enable fault handling */
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int (*enable_faulting)(void);
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/* Get the irqdomain associated the IOMMU device */
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struct irq_domain *(*get_ir_irq_domain)(struct irq_alloc_info *);
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/* Get the MSI irqdomain associated with the IOMMU device */
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struct irq_domain *(*get_irq_domain)(struct irq_alloc_info *);
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};
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extern struct irq_remap_ops intel_irq_remap_ops;
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extern struct irq_remap_ops amd_iommu_irq_ops;
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extern struct irq_remap_ops hyperv_irq_remap_ops;
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#else /* CONFIG_IRQ_REMAP */
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#define irq_remapping_enabled 0
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#define irq_remap_broken 0
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#define disable_irq_post 1
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#endif /* CONFIG_IRQ_REMAP */
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#endif /* __IRQ_REMAPPING_H */
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