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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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dc9eeff84c
Move all error messages from IP specific code into the common helper. This way we now uses the ring name in the messages instead of the index and note which device is affected as well. Also cleanup error handling in the IP specific code and consequently use ETIMEDOUT when the ring test timed out. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
529 lines
14 KiB
C
529 lines
14 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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* Christian König
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*/
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include <linux/debugfs.h>
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#include <drm/drmP.h>
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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#include "atom.h"
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/*
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* Rings
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* Most engines on the GPU are fed via ring buffers. Ring
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* buffers are areas of GPU accessible memory that the host
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* writes commands into and the GPU reads commands out of.
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* There is a rptr (read pointer) that determines where the
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* GPU is currently reading, and a wptr (write pointer)
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* which determines where the host has written. When the
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* pointers are equal, the ring is idle. When the host
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* writes commands to the ring buffer, it increments the
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* wptr. The GPU then starts fetching commands and executes
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* them until the pointers are equal again.
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*/
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static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
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struct amdgpu_ring *ring);
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static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring);
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/**
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* amdgpu_ring_alloc - allocate space on the ring buffer
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*
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* @adev: amdgpu_device pointer
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* @ring: amdgpu_ring structure holding ring information
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* @ndw: number of dwords to allocate in the ring buffer
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*
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* Allocate @ndw dwords in the ring buffer (all asics).
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* Returns 0 on success, error on failure.
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*/
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int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
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{
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/* Align requested size with padding so unlock_commit can
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* pad safely */
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ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
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/* Make sure we aren't trying to allocate more space
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* than the maximum for one submission
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*/
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if (WARN_ON_ONCE(ndw > ring->max_dw))
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return -ENOMEM;
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ring->count_dw = ndw;
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ring->wptr_old = ring->wptr;
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if (ring->funcs->begin_use)
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ring->funcs->begin_use(ring);
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return 0;
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}
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/** amdgpu_ring_insert_nop - insert NOP packets
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*
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* @ring: amdgpu_ring structure holding ring information
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* @count: the number of NOP packets to insert
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*
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* This is the generic insert_nop function for rings except SDMA
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*/
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void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
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{
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int i;
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for (i = 0; i < count; i++)
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amdgpu_ring_write(ring, ring->funcs->nop);
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}
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/** amdgpu_ring_generic_pad_ib - pad IB with NOP packets
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*
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* @ring: amdgpu_ring structure holding ring information
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* @ib: IB to add NOP packets to
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*
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* This is the generic pad_ib function for rings except SDMA
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*/
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void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
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{
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while (ib->length_dw & ring->funcs->align_mask)
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ib->ptr[ib->length_dw++] = ring->funcs->nop;
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}
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/**
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* amdgpu_ring_commit - tell the GPU to execute the new
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* commands on the ring buffer
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*
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* @adev: amdgpu_device pointer
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* @ring: amdgpu_ring structure holding ring information
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*
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* Update the wptr (write pointer) to tell the GPU to
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* execute new commands on the ring buffer (all asics).
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*/
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void amdgpu_ring_commit(struct amdgpu_ring *ring)
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{
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uint32_t count;
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/* We pad to match fetch size */
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count = ring->funcs->align_mask + 1 -
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(ring->wptr & ring->funcs->align_mask);
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count %= ring->funcs->align_mask + 1;
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ring->funcs->insert_nop(ring, count);
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mb();
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amdgpu_ring_set_wptr(ring);
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if (ring->funcs->end_use)
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ring->funcs->end_use(ring);
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}
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/**
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* amdgpu_ring_undo - reset the wptr
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*
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* @ring: amdgpu_ring structure holding ring information
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*
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* Reset the driver's copy of the wptr (all asics).
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*/
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void amdgpu_ring_undo(struct amdgpu_ring *ring)
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{
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ring->wptr = ring->wptr_old;
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if (ring->funcs->end_use)
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ring->funcs->end_use(ring);
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}
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/**
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* amdgpu_ring_priority_put - restore a ring's priority
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*
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* @ring: amdgpu_ring structure holding the information
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* @priority: target priority
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*
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* Release a request for executing at @priority
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*/
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void amdgpu_ring_priority_put(struct amdgpu_ring *ring,
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enum drm_sched_priority priority)
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{
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int i;
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if (!ring->funcs->set_priority)
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return;
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if (atomic_dec_return(&ring->num_jobs[priority]) > 0)
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return;
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/* no need to restore if the job is already at the lowest priority */
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if (priority == DRM_SCHED_PRIORITY_NORMAL)
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return;
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mutex_lock(&ring->priority_mutex);
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/* something higher prio is executing, no need to decay */
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if (ring->priority > priority)
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goto out_unlock;
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/* decay priority to the next level with a job available */
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for (i = priority; i >= DRM_SCHED_PRIORITY_MIN; i--) {
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if (i == DRM_SCHED_PRIORITY_NORMAL
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|| atomic_read(&ring->num_jobs[i])) {
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ring->priority = i;
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ring->funcs->set_priority(ring, i);
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break;
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}
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}
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out_unlock:
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mutex_unlock(&ring->priority_mutex);
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}
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/**
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* amdgpu_ring_priority_get - change the ring's priority
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*
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* @ring: amdgpu_ring structure holding the information
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* @priority: target priority
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*
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* Request a ring's priority to be raised to @priority (refcounted).
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*/
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void amdgpu_ring_priority_get(struct amdgpu_ring *ring,
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enum drm_sched_priority priority)
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{
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if (!ring->funcs->set_priority)
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return;
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if (atomic_inc_return(&ring->num_jobs[priority]) <= 0)
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return;
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mutex_lock(&ring->priority_mutex);
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if (priority <= ring->priority)
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goto out_unlock;
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ring->priority = priority;
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ring->funcs->set_priority(ring, priority);
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out_unlock:
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mutex_unlock(&ring->priority_mutex);
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}
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/**
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* amdgpu_ring_init - init driver ring struct.
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*
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* @adev: amdgpu_device pointer
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* @ring: amdgpu_ring structure holding ring information
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* @max_ndw: maximum number of dw for ring alloc
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* @nop: nop packet for this ring
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*
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* Initialize the driver information for the selected ring (all asics).
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* Returns 0 on success, error on failure.
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*/
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int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
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unsigned max_dw, struct amdgpu_irq_src *irq_src,
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unsigned irq_type)
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{
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int r, i;
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int sched_hw_submission = amdgpu_sched_hw_submission;
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/* Set the hw submission limit higher for KIQ because
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* it's used for a number of gfx/compute tasks by both
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* KFD and KGD which may have outstanding fences and
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* it doesn't really use the gpu scheduler anyway;
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* KIQ tasks get submitted directly to the ring.
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*/
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if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
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sched_hw_submission = max(sched_hw_submission, 256);
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if (ring->adev == NULL) {
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if (adev->num_rings >= AMDGPU_MAX_RINGS)
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return -EINVAL;
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ring->adev = adev;
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ring->idx = adev->num_rings++;
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adev->rings[ring->idx] = ring;
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r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission);
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if (r)
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return r;
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}
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r = amdgpu_device_wb_get(adev, &ring->rptr_offs);
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if (r) {
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dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
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return r;
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}
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r = amdgpu_device_wb_get(adev, &ring->wptr_offs);
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if (r) {
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dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
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return r;
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}
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r = amdgpu_device_wb_get(adev, &ring->fence_offs);
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if (r) {
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dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
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return r;
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}
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r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs);
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if (r) {
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dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
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return r;
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}
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ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4);
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ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs];
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/* always set cond_exec_polling to CONTINUE */
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*ring->cond_exe_cpu_addr = 1;
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r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
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if (r) {
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dev_err(adev->dev, "failed initializing fences (%d).\n", r);
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return r;
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}
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ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);
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ring->buf_mask = (ring->ring_size / 4) - 1;
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ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
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0xffffffffffffffff : ring->buf_mask;
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/* Allocate ring buffer */
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if (ring->ring_obj == NULL) {
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r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_dw, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_GTT,
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&ring->ring_obj,
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&ring->gpu_addr,
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(void **)&ring->ring);
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if (r) {
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dev_err(adev->dev, "(%d) ring create failed\n", r);
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return r;
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}
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amdgpu_ring_clear_ring(ring);
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}
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ring->max_dw = max_dw;
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ring->priority = DRM_SCHED_PRIORITY_NORMAL;
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mutex_init(&ring->priority_mutex);
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for (i = 0; i < DRM_SCHED_PRIORITY_MAX; ++i)
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atomic_set(&ring->num_jobs[i], 0);
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if (amdgpu_debugfs_ring_init(adev, ring)) {
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DRM_ERROR("Failed to register debugfs file for rings !\n");
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}
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return 0;
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}
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/**
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* amdgpu_ring_fini - tear down the driver ring struct.
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*
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* @adev: amdgpu_device pointer
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* @ring: amdgpu_ring structure holding ring information
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*
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* Tear down the driver information for the selected ring (all asics).
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*/
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void amdgpu_ring_fini(struct amdgpu_ring *ring)
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{
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ring->sched.ready = false;
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/* Not to finish a ring which is not initialized */
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if (!(ring->adev) || !(ring->adev->rings[ring->idx]))
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return;
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amdgpu_device_wb_free(ring->adev, ring->rptr_offs);
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amdgpu_device_wb_free(ring->adev, ring->wptr_offs);
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amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs);
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amdgpu_device_wb_free(ring->adev, ring->fence_offs);
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amdgpu_bo_free_kernel(&ring->ring_obj,
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&ring->gpu_addr,
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(void **)&ring->ring);
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amdgpu_debugfs_ring_fini(ring);
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dma_fence_put(ring->vmid_wait);
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ring->vmid_wait = NULL;
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ring->me = 0;
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ring->adev->rings[ring->idx] = NULL;
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}
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/**
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* amdgpu_ring_emit_reg_write_reg_wait_helper - ring helper
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*
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* @adev: amdgpu_device pointer
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* @reg0: register to write
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* @reg1: register to wait on
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* @ref: reference value to write/wait on
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* @mask: mask to wait on
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*
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* Helper for rings that don't support write and wait in a
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* single oneshot packet.
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*/
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void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
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uint32_t reg0, uint32_t reg1,
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uint32_t ref, uint32_t mask)
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{
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amdgpu_ring_emit_wreg(ring, reg0, ref);
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amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
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}
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/**
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* amdgpu_ring_soft_recovery - try to soft recover a ring lockup
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*
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* @ring: ring to try the recovery on
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* @vmid: VMID we try to get going again
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* @fence: timedout fence
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*
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* Tries to get a ring proceeding again when it is stuck.
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*/
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bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
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struct dma_fence *fence)
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{
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ktime_t deadline = ktime_add_us(ktime_get(), 10000);
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if (!ring->funcs->soft_recovery)
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return false;
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atomic_inc(&ring->adev->gpu_reset_counter);
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while (!dma_fence_is_signaled(fence) &&
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ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0)
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ring->funcs->soft_recovery(ring, vmid);
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return dma_fence_is_signaled(fence);
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}
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/*
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* Debugfs info
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*/
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#if defined(CONFIG_DEBUG_FS)
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/* Layout of file is 12 bytes consisting of
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* - rptr
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* - wptr
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* - driver's copy of wptr
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*
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* followed by n-words of ring data
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*/
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static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
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size_t size, loff_t *pos)
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{
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struct amdgpu_ring *ring = file_inode(f)->i_private;
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int r, i;
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uint32_t value, result, early[3];
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if (*pos & 3 || size & 3)
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return -EINVAL;
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result = 0;
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if (*pos < 12) {
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early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask;
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early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
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early[2] = ring->wptr & ring->buf_mask;
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for (i = *pos / 4; i < 3 && size; i++) {
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r = put_user(early[i], (uint32_t *)buf);
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if (r)
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return r;
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buf += 4;
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result += 4;
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size -= 4;
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*pos += 4;
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}
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}
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while (size) {
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if (*pos >= (ring->ring_size + 12))
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return result;
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value = ring->ring[(*pos - 12)/4];
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r = put_user(value, (uint32_t*)buf);
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if (r)
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return r;
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buf += 4;
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result += 4;
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size -= 4;
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*pos += 4;
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}
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return result;
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}
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static const struct file_operations amdgpu_debugfs_ring_fops = {
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.owner = THIS_MODULE,
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.read = amdgpu_debugfs_ring_read,
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.llseek = default_llseek
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};
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#endif
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static int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
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struct amdgpu_ring *ring)
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{
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#if defined(CONFIG_DEBUG_FS)
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struct drm_minor *minor = adev->ddev->primary;
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struct dentry *ent, *root = minor->debugfs_root;
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char name[32];
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sprintf(name, "amdgpu_ring_%s", ring->name);
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ent = debugfs_create_file(name,
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S_IFREG | S_IRUGO, root,
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ring, &amdgpu_debugfs_ring_fops);
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if (!ent)
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return -ENOMEM;
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i_size_write(ent->d_inode, ring->ring_size + 12);
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ring->ent = ent;
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#endif
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return 0;
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}
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|
static void amdgpu_debugfs_ring_fini(struct amdgpu_ring *ring)
|
|
{
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
debugfs_remove(ring->ent);
|
|
#endif
|
|
}
|
|
|
|
/**
|
|
* amdgpu_ring_test_helper - tests ring and set sched readiness status
|
|
*
|
|
* @ring: ring to try the recovery on
|
|
*
|
|
* Tests ring and set sched readiness status
|
|
*
|
|
* Returns 0 on success, error on failure.
|
|
*/
|
|
int amdgpu_ring_test_helper(struct amdgpu_ring *ring)
|
|
{
|
|
struct amdgpu_device *adev = ring->adev;
|
|
int r;
|
|
|
|
r = amdgpu_ring_test_ring(ring);
|
|
if (r)
|
|
DRM_DEV_ERROR(adev->dev, "ring %s test failed (%d)\n",
|
|
ring->name, r);
|
|
else
|
|
DRM_DEV_DEBUG(adev->dev, "ring test on %s succeeded\n",
|
|
ring->name);
|
|
|
|
ring->sched.ready = !r;
|
|
return r;
|
|
}
|