mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
287 lines
7.0 KiB
C
287 lines
7.0 KiB
C
/*
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* Copyright 2001 MontaVista Software Inc.
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* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
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*
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* arch/mips/ddb5xxx/ddb5476/pci_ops.c
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* Define the pci_ops for DB5477.
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*
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* Much of the code is derived from the original DDB5074 port by
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* Geert Uytterhoeven <geert@sonycom.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <asm/addrspace.h>
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#include <asm/debug.h>
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#include <asm/ddb5xxx/ddb5xxx.h>
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/*
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* config_swap structure records what set of pdar/pmr are used
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* to access pci config space. It also provides a place hold the
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* original values for future restoring.
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*/
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struct pci_config_swap {
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u32 pdar;
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u32 pmr;
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u32 config_base;
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u32 config_size;
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u32 pdar_backup;
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u32 pmr_backup;
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};
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/*
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* On DDB5476, we have one set of swap registers
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*/
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struct pci_config_swap ext_pci_swap = {
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DDB_PCIW0,
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DDB_PCIINIT0,
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DDB_PCI_CONFIG_BASE,
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DDB_PCI_CONFIG_SIZE
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};
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static int pci_config_workaround = 1;
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/*
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* access config space
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*/
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static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */
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u32 slot_num)
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{
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u32 pci_addr = 0;
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u32 pciinit_offset = 0;
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u32 virt_addr = swap->config_base;
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u32 option;
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if (pci_config_workaround) {
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/* [jsun] work around Vrc5476 controller itself, returnning
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* slot 0 essentially makes vrc5476 invisible
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*/
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if (slot_num == 12)
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slot_num = 0;
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#if 0
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/* BUG : skip P2P bridge for now */
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if (slot_num == 5)
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slot_num = 0;
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#endif
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} else {
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/* now we have to be hornest, returning the true
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* PCI config headers for vrc5476
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*/
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if (slot_num == 12) {
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swap->pdar_backup = ddb_in32(swap->pdar);
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swap->pmr_backup = ddb_in32(swap->pmr);
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return DDB_BASE + DDB_PCI_BASE;
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}
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}
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/* minimum pdar (window) size is 2MB */
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db_assert(swap->config_size >= (2 << 20));
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db_assert(slot_num < (1 << 5));
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db_assert(bus < (1 << 8));
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/* backup registers */
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swap->pdar_backup = ddb_in32(swap->pdar);
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swap->pmr_backup = ddb_in32(swap->pmr);
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/* set the pdar (pci window) register */
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ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */
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0, /* not on local memory bus */
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0); /* not visible from PCI bus (N/A) */
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/*
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* calcuate the absolute pci config addr;
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* according to the spec, we start scanning from adr:11 (0x800)
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*/
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if (bus == 0) {
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/* type 0 config */
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pci_addr = 0x800 << slot_num;
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} else {
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/* type 1 config */
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pci_addr = (bus << 16) | (slot_num << 11);
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/* panic("ddb_access_config_base: we don't support type 1 config Yet"); */
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}
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/*
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* if pci_addr is less than pci config window size, we set
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* pciinit_offset to 0 and adjust the virt_address.
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* Otherwise we will try to adjust pciinit_offset.
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*/
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if (pci_addr < swap->config_size) {
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virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
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pciinit_offset = 0;
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} else {
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db_assert((pci_addr & (swap->config_size - 1)) == 0);
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virt_addr = KSEG1ADDR(swap->config_base);
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pciinit_offset = pci_addr;
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}
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/* set the pmr register */
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option = DDB_PCI_ACCESS_32;
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if (bus != 0)
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option |= DDB_PCI_CFGTYPE1;
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ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option);
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return virt_addr;
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}
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static inline void ddb_close_config_base(struct pci_config_swap *swap)
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{
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ddb_out32(swap->pdar, swap->pdar_backup);
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ddb_out32(swap->pmr, swap->pmr_backup);
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}
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static int read_config_dword(struct pci_config_swap *swap,
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struct pci_dev *dev, u32 where, u32 * val)
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{
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u32 bus, slot_num, func_num;
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u32 base;
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db_assert((where & 3) == 0);
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db_assert(where < (1 << 8));
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/* check if the bus is top-level */
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if (dev->bus->parent != NULL) {
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bus = dev->bus->number;
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db_assert(bus != 0);
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} else {
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bus = 0;
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}
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slot_num = PCI_SLOT(dev->devfn);
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func_num = PCI_FUNC(dev->devfn);
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base = ddb_access_config_base(swap, bus, slot_num);
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*val = *(volatile u32 *) (base + (func_num << 8) + where);
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ddb_close_config_base(swap);
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return PCIBIOS_SUCCESSFUL;
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}
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static int read_config_word(struct pci_config_swap *swap,
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struct pci_dev *dev, u32 where, u16 * val)
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{
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int status;
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u32 result;
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db_assert((where & 1) == 0);
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status = read_config_dword(swap, dev, where & ~3, &result);
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if (where & 2)
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result >>= 16;
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*val = result & 0xffff;
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return status;
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}
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static int read_config_byte(struct pci_config_swap *swap,
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struct pci_dev *dev, u32 where, u8 * val)
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{
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int status;
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u32 result;
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status = read_config_dword(swap, dev, where & ~3, &result);
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if (where & 1)
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result >>= 8;
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if (where & 2)
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result >>= 16;
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*val = result & 0xff;
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return status;
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}
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static int write_config_dword(struct pci_config_swap *swap,
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struct pci_dev *dev, u32 where, u32 val)
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{
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u32 bus, slot_num, func_num;
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u32 base;
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db_assert((where & 3) == 0);
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db_assert(where < (1 << 8));
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/* check if the bus is top-level */
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if (dev->bus->parent != NULL) {
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bus = dev->bus->number;
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db_assert(bus != 0);
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} else {
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bus = 0;
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}
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slot_num = PCI_SLOT(dev->devfn);
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func_num = PCI_FUNC(dev->devfn);
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base = ddb_access_config_base(swap, bus, slot_num);
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*(volatile u32 *) (base + (func_num << 8) + where) = val;
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ddb_close_config_base(swap);
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return PCIBIOS_SUCCESSFUL;
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}
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static int write_config_word(struct pci_config_swap *swap,
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struct pci_dev *dev, u32 where, u16 val)
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{
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int status, shift = 0;
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u32 result;
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db_assert((where & 1) == 0);
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status = read_config_dword(swap, dev, where & ~3, &result);
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if (status != PCIBIOS_SUCCESSFUL)
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return status;
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if (where & 2)
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shift += 16;
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result &= ~(0xffff << shift);
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result |= val << shift;
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return write_config_dword(swap, dev, where & ~3, result);
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}
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static int write_config_byte(struct pci_config_swap *swap,
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struct pci_dev *dev, u32 where, u8 val)
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{
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int status, shift = 0;
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u32 result;
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status = read_config_dword(swap, dev, where & ~3, &result);
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if (status != PCIBIOS_SUCCESSFUL)
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return status;
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if (where & 2)
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shift += 16;
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if (where & 1)
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shift += 8;
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result &= ~(0xff << shift);
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result |= val << shift;
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return write_config_dword(swap, dev, where & ~3, result);
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}
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#define MAKE_PCI_OPS(prefix, rw, unitname, unittype, pciswap) \
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static int prefix##_##rw##_config_##unitname(struct pci_dev *dev, int where, unittype val) \
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{ \
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return rw##_config_##unitname(pciswap, \
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dev, \
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where, \
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val); \
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}
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MAKE_PCI_OPS(extpci, read, byte, u8 *, &ext_pci_swap)
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MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap)
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MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap)
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MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap)
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MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap)
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MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap)
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struct pci_ops ddb5476_ext_pci_ops = {
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extpci_read_config_byte,
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extpci_read_config_word,
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extpci_read_config_dword,
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extpci_write_config_byte,
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extpci_write_config_word,
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extpci_write_config_dword
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};
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