mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 15:55:40 +07:00
b4d4b0b7de
on all platforms back to HSW. As well many other fix and improvements, Including: - Use GEM suspend when aborting initialization (Chris) - Change i915_gem_fault to return vm_fault_t (Chris) - Expand VMA to Non gem object entities (Chris) - Improve logs for load failure, but quite logging on fault injection to avoid noise on CI (Chris) - Other page directory handling fixes and improvements for gen6 (Chris) - Other gtt clean-up removing redundancies and unused checks (Chris) - Reorder aliasing ppgtt fini (Chris) - Refactor of unsetting obg->mm.pages (Chris) - Apply batch location restrictions before pinning (Chris) - Ringbuffer fixes for context restore (Chris) - Execlist fixes on freeing error pointer on allocation error (Chris) - Make closing request flush mandatory (Chris) - Move GEM sanitize from resume_early to resume (Chris) - Improve debug dumps (Chris) - Silent compiler for selftest (Chris) - Other execlists changes to improve hangcheck and reset. - Many gtt page directory fixes and improvements (Chris) - Reorg context workarounds (Chris) - Avoid ERR_PTR dereference on selftest (Chris) Other GEM related work: - Stop trying to reset GPU if reset failed (Mika) - Add HW workaround for KBL to fix GPU reset (Mika) - Fix context ban and hang accounting for client (Mika) - Fixes on OA perf (Michel, Jani) - Refactor on GuC log mechanisms (Piotr) - Enable provoking vertex fix on Gen9 system (Kenneth) More ICL patches for Display enabling: - ICL - 10-bit support for HDMI (RK) - ICL - Start adding TBT PLL (Paulo) - ICL - DDI HDMK level selection (Manasi) - ICL - GMBUS GPIO pin mapping fix (Mahesh) - ICL - Adding DP_AUX_E support (James) - ICL - Display interrupts handling (DK) Other display fixes and improvements: - Fix sprite destination color keying on SKL+ (Ville) - Fixes and improvements on PCH detection, specially for non PCH systems (Jani) - Document PCH_NOP (Lucas) - Allow DBLSCAN user modes with eDP/LVDS/DSI (Ville) - Opregion and ACPI cleanup and organization (Jani) - Kill delays when activation psr (Rodrigo) - ...and a consequent fix of the psr activation flow (DK) - Fix HDMI infoframe setting (Imre) - Fix Display interrupts and modes on old gens (Ville) - Start switching to kernel unsigned int types (Jani) - Introduction to Amber Lake and Whiskey Lake platforms (Jose) - Audio clock fixes for HBR3 (RK) - Standardize i915_reg.h definitions according to our doc and checkpatch (Paulo) - Remove unused timespec_to_jiffies_timeout function (Arnd) - Increase the scope of PSR wake fix for other VBTs out there (Vathsala) - Improve debug msgs with prop name/id (Ville) - Other clean up on unecessary cursor size defines (Ville) - Enforce max hdisplay/hblank_start limits on HSW/BDW (Ville) - Make ELD pointers constant (Jani) - Fix for PSR VBT parse (Colin) - Add warn about unsupported CDCLK rates (Imre) -----BEGIN PGP SIGNATURE----- iQEcBAABAgAGBQJbKsMqAAoJEPpiX2QO6xPKI64H/0dHkMxw7/D83eODTJteDFBN h3tdBnLFlPfeG3ZWDeSs04/dM4e9YacMN7v53j1ia4eW/F1ms0TLcegcuPqYafTW H8fhwGB2B5gmr5hLfh5joQkxvaucQMFdg95fWRqir93VrKvVJAJEYNcaiGniejDf qqiZue6DgAzli0zjAprfbQsnJ17TyRtnxm8lLIcFcHPoayHBzAUBZQEP6cA5qe/Y /2ahGfkYOVVWY08DHaioDBOLUEUbxCC1AvMlv9VbtKmyPoQjTIW/1iTq0RRxDoGb BwfDvigSiFAmpYEfVENB0qUd9e/0WhMboSnMrfzEcF2yUn4xoJx5nbmkRFkr1jI= =mfO6 -----END PGP SIGNATURE----- Merge tag 'drm-intel-next-2018-06-20' of git://anongit.freedesktop.org/drm/drm-intel into drm-next Chris is doing many reworks that allow us to get full-ppgtt supported on all platforms back to HSW. As well many other fix and improvements, Including: - Use GEM suspend when aborting initialization (Chris) - Change i915_gem_fault to return vm_fault_t (Chris) - Expand VMA to Non gem object entities (Chris) - Improve logs for load failure, but quite logging on fault injection to avoid noise on CI (Chris) - Other page directory handling fixes and improvements for gen6 (Chris) - Other gtt clean-up removing redundancies and unused checks (Chris) - Reorder aliasing ppgtt fini (Chris) - Refactor of unsetting obg->mm.pages (Chris) - Apply batch location restrictions before pinning (Chris) - Ringbuffer fixes for context restore (Chris) - Execlist fixes on freeing error pointer on allocation error (Chris) - Make closing request flush mandatory (Chris) - Move GEM sanitize from resume_early to resume (Chris) - Improve debug dumps (Chris) - Silent compiler for selftest (Chris) - Other execlists changes to improve hangcheck and reset. - Many gtt page directory fixes and improvements (Chris) - Reorg context workarounds (Chris) - Avoid ERR_PTR dereference on selftest (Chris) Other GEM related work: - Stop trying to reset GPU if reset failed (Mika) - Add HW workaround for KBL to fix GPU reset (Mika) - Fix context ban and hang accounting for client (Mika) - Fixes on OA perf (Michel, Jani) - Refactor on GuC log mechanisms (Piotr) - Enable provoking vertex fix on Gen9 system (Kenneth) More ICL patches for Display enabling: - ICL - 10-bit support for HDMI (RK) - ICL - Start adding TBT PLL (Paulo) - ICL - DDI HDMK level selection (Manasi) - ICL - GMBUS GPIO pin mapping fix (Mahesh) - ICL - Adding DP_AUX_E support (James) - ICL - Display interrupts handling (DK) Other display fixes and improvements: - Fix sprite destination color keying on SKL+ (Ville) - Fixes and improvements on PCH detection, specially for non PCH systems (Jani) - Document PCH_NOP (Lucas) - Allow DBLSCAN user modes with eDP/LVDS/DSI (Ville) - Opregion and ACPI cleanup and organization (Jani) - Kill delays when activation psr (Rodrigo) - ...and a consequent fix of the psr activation flow (DK) - Fix HDMI infoframe setting (Imre) - Fix Display interrupts and modes on old gens (Ville) - Start switching to kernel unsigned int types (Jani) - Introduction to Amber Lake and Whiskey Lake platforms (Jose) - Audio clock fixes for HBR3 (RK) - Standardize i915_reg.h definitions according to our doc and checkpatch (Paulo) - Remove unused timespec_to_jiffies_timeout function (Arnd) - Increase the scope of PSR wake fix for other VBTs out there (Vathsala) - Improve debug msgs with prop name/id (Ville) - Other clean up on unecessary cursor size defines (Ville) - Enforce max hdisplay/hblank_start limits on HSW/BDW (Ville) - Make ELD pointers constant (Jani) - Fix for PSR VBT parse (Colin) - Add warn about unsupported CDCLK rates (Imre) Signed-off-by: Dave Airlie <airlied@redhat.com> # gpg: Signature made Thu 21 Jun 2018 07:12:10 AM AEST # gpg: using RSA key FA625F640EEB13CA # gpg: Good signature from "Rodrigo Vivi <rodrigo.vivi@intel.com>" # gpg: aka "Rodrigo Vivi <rodrigo.vivi@gmail.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6D20 7068 EEDD 6509 1C2C E2A3 FA62 5F64 0EEB 13CA Link: https://patchwork.freedesktop.org/patch/msgid/20180625165622.GA21761@intel.com
291 lines
7.2 KiB
C
291 lines
7.2 KiB
C
/*
|
|
* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice (including the next
|
|
* paragraph) shall be included in all copies or substantial portions of the
|
|
* Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
|
* SOFTWARE.
|
|
*
|
|
* Authors:
|
|
* Ke Yu
|
|
* Kevin Tian <kevin.tian@intel.com>
|
|
* Dexuan Cui
|
|
*
|
|
* Contributors:
|
|
* Tina Zhang <tina.zhang@intel.com>
|
|
* Min He <min.he@intel.com>
|
|
* Niu Bing <bing.niu@intel.com>
|
|
* Zhi Wang <zhi.a.wang@intel.com>
|
|
*
|
|
*/
|
|
|
|
#include "i915_drv.h"
|
|
#include "gvt.h"
|
|
|
|
/**
|
|
* intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset
|
|
* @vgpu: a vGPU
|
|
*
|
|
* Returns:
|
|
* Zero on success, negative error code if failed
|
|
*/
|
|
int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa)
|
|
{
|
|
u64 gttmmio_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);
|
|
return gpa - gttmmio_gpa;
|
|
}
|
|
|
|
#define reg_is_mmio(gvt, reg) \
|
|
(reg >= 0 && reg < gvt->device_info.mmio_size)
|
|
|
|
#define reg_is_gtt(gvt, reg) \
|
|
(reg >= gvt->device_info.gtt_start_offset \
|
|
&& reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt))
|
|
|
|
static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, uint64_t pa,
|
|
void *p_data, unsigned int bytes, bool read)
|
|
{
|
|
struct intel_gvt *gvt = NULL;
|
|
void *pt = NULL;
|
|
unsigned int offset = 0;
|
|
|
|
if (!vgpu || !p_data)
|
|
return;
|
|
|
|
gvt = vgpu->gvt;
|
|
mutex_lock(&vgpu->vgpu_lock);
|
|
offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
|
|
if (reg_is_mmio(gvt, offset)) {
|
|
if (read)
|
|
intel_vgpu_default_mmio_read(vgpu, offset, p_data,
|
|
bytes);
|
|
else
|
|
intel_vgpu_default_mmio_write(vgpu, offset, p_data,
|
|
bytes);
|
|
} else if (reg_is_gtt(gvt, offset)) {
|
|
offset -= gvt->device_info.gtt_start_offset;
|
|
pt = vgpu->gtt.ggtt_mm->ggtt_mm.virtual_ggtt + offset;
|
|
if (read)
|
|
memcpy(p_data, pt, bytes);
|
|
else
|
|
memcpy(pt, p_data, bytes);
|
|
|
|
}
|
|
mutex_unlock(&vgpu->vgpu_lock);
|
|
}
|
|
|
|
/**
|
|
* intel_vgpu_emulate_mmio_read - emulate MMIO read
|
|
* @vgpu: a vGPU
|
|
* @pa: guest physical address
|
|
* @p_data: data return buffer
|
|
* @bytes: access data length
|
|
*
|
|
* Returns:
|
|
* Zero on success, negative error code if failed
|
|
*/
|
|
int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
|
|
void *p_data, unsigned int bytes)
|
|
{
|
|
struct intel_gvt *gvt = vgpu->gvt;
|
|
unsigned int offset = 0;
|
|
int ret = -EINVAL;
|
|
|
|
if (vgpu->failsafe) {
|
|
failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true);
|
|
return 0;
|
|
}
|
|
mutex_lock(&vgpu->vgpu_lock);
|
|
|
|
offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
|
|
|
|
if (WARN_ON(bytes > 8))
|
|
goto err;
|
|
|
|
if (reg_is_gtt(gvt, offset)) {
|
|
if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
|
|
goto err;
|
|
if (WARN_ON(bytes != 4 && bytes != 8))
|
|
goto err;
|
|
if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
|
|
goto err;
|
|
|
|
ret = intel_vgpu_emulate_ggtt_mmio_read(vgpu, offset,
|
|
p_data, bytes);
|
|
if (ret)
|
|
goto err;
|
|
goto out;
|
|
}
|
|
|
|
if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
|
|
ret = intel_gvt_hypervisor_read_gpa(vgpu, pa, p_data, bytes);
|
|
goto out;
|
|
}
|
|
|
|
if (WARN_ON(!reg_is_mmio(gvt, offset + bytes - 1)))
|
|
goto err;
|
|
|
|
if (!intel_gvt_mmio_is_unalign(gvt, offset)) {
|
|
if (WARN_ON(!IS_ALIGNED(offset, bytes)))
|
|
goto err;
|
|
}
|
|
|
|
ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true);
|
|
if (ret < 0)
|
|
goto err;
|
|
|
|
intel_gvt_mmio_set_accessed(gvt, offset);
|
|
ret = 0;
|
|
goto out;
|
|
|
|
err:
|
|
gvt_vgpu_err("fail to emulate MMIO read %08x len %d\n",
|
|
offset, bytes);
|
|
out:
|
|
mutex_unlock(&vgpu->vgpu_lock);
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* intel_vgpu_emulate_mmio_write - emulate MMIO write
|
|
* @vgpu: a vGPU
|
|
* @pa: guest physical address
|
|
* @p_data: write data buffer
|
|
* @bytes: access data length
|
|
*
|
|
* Returns:
|
|
* Zero on success, negative error code if failed
|
|
*/
|
|
int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa,
|
|
void *p_data, unsigned int bytes)
|
|
{
|
|
struct intel_gvt *gvt = vgpu->gvt;
|
|
unsigned int offset = 0;
|
|
int ret = -EINVAL;
|
|
|
|
if (vgpu->failsafe) {
|
|
failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, false);
|
|
return 0;
|
|
}
|
|
|
|
mutex_lock(&vgpu->vgpu_lock);
|
|
|
|
offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
|
|
|
|
if (WARN_ON(bytes > 8))
|
|
goto err;
|
|
|
|
if (reg_is_gtt(gvt, offset)) {
|
|
if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
|
|
goto err;
|
|
if (WARN_ON(bytes != 4 && bytes != 8))
|
|
goto err;
|
|
if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
|
|
goto err;
|
|
|
|
ret = intel_vgpu_emulate_ggtt_mmio_write(vgpu, offset,
|
|
p_data, bytes);
|
|
if (ret)
|
|
goto err;
|
|
goto out;
|
|
}
|
|
|
|
if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
|
|
ret = intel_gvt_hypervisor_write_gpa(vgpu, pa, p_data, bytes);
|
|
goto out;
|
|
}
|
|
|
|
ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false);
|
|
if (ret < 0)
|
|
goto err;
|
|
|
|
intel_gvt_mmio_set_accessed(gvt, offset);
|
|
ret = 0;
|
|
goto out;
|
|
err:
|
|
gvt_vgpu_err("fail to emulate MMIO write %08x len %d\n", offset,
|
|
bytes);
|
|
out:
|
|
mutex_unlock(&vgpu->vgpu_lock);
|
|
return ret;
|
|
}
|
|
|
|
|
|
/**
|
|
* intel_vgpu_reset_mmio - reset virtual MMIO space
|
|
* @vgpu: a vGPU
|
|
*
|
|
*/
|
|
void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
|
|
{
|
|
struct intel_gvt *gvt = vgpu->gvt;
|
|
const struct intel_gvt_device_info *info = &gvt->device_info;
|
|
void *mmio = gvt->firmware.mmio;
|
|
|
|
if (dmlr) {
|
|
memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);
|
|
memcpy(vgpu->mmio.sreg, mmio, info->mmio_size);
|
|
|
|
vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;
|
|
|
|
/* set the bit 0:2(Core C-State ) to C0 */
|
|
vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0;
|
|
} else {
|
|
#define GVT_GEN8_MMIO_RESET_OFFSET (0x44200)
|
|
/* only reset the engine related, so starting with 0x44200
|
|
* interrupt include DE,display mmio related will not be
|
|
* touched
|
|
*/
|
|
memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
|
|
memcpy(vgpu->mmio.sreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
|
|
}
|
|
|
|
}
|
|
|
|
/**
|
|
* intel_vgpu_init_mmio - init MMIO space
|
|
* @vgpu: a vGPU
|
|
*
|
|
* Returns:
|
|
* Zero on success, negative error code if failed
|
|
*/
|
|
int intel_vgpu_init_mmio(struct intel_vgpu *vgpu)
|
|
{
|
|
const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
|
|
|
|
vgpu->mmio.vreg = vzalloc(array_size(info->mmio_size, 2));
|
|
if (!vgpu->mmio.vreg)
|
|
return -ENOMEM;
|
|
|
|
vgpu->mmio.sreg = vgpu->mmio.vreg + info->mmio_size;
|
|
|
|
intel_vgpu_reset_mmio(vgpu, true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* intel_vgpu_clean_mmio - clean MMIO space
|
|
* @vgpu: a vGPU
|
|
*
|
|
*/
|
|
void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu)
|
|
{
|
|
vfree(vgpu->mmio.vreg);
|
|
vgpu->mmio.vreg = vgpu->mmio.sreg = NULL;
|
|
}
|