mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a556c76adc
Add a driver for Microsemi Ocelot Ethernet switch support. This makes two modules: mscc_ocelot_common handles all the common features that doesn't depend on how the switch is integrated in the SoC. Currently, it handles offloading bridging to the hardware. ocelot_io.c handles register accesses. This is unfortunately needed because the register layout is packed and then depends on the number of ports available on the switch. The register definition files are automatically generated. ocelot_board handles the switch integration on the SoC and on the board. Frame injection and extraction to/from the CPU port is currently done using register accesses which is quite slow. DMA is possible but the port is not able to absorb the whole switch bandwidth. Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
117 lines
2.6 KiB
C
117 lines
2.6 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Microsemi Ocelot Switch driver
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*
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* Copyright (c) 2017 Microsemi Corporation
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*/
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include "ocelot.h"
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u32 __ocelot_read_ix(struct ocelot *ocelot, u32 reg, u32 offset)
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{
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u16 target = reg >> TARGET_OFFSET;
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u32 val;
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WARN_ON(!target);
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regmap_read(ocelot->targets[target],
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ocelot->map[target][reg & REG_MASK] + offset, &val);
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return val;
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}
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EXPORT_SYMBOL(__ocelot_read_ix);
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void __ocelot_write_ix(struct ocelot *ocelot, u32 val, u32 reg, u32 offset)
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{
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u16 target = reg >> TARGET_OFFSET;
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WARN_ON(!target);
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regmap_write(ocelot->targets[target],
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ocelot->map[target][reg & REG_MASK] + offset, val);
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}
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EXPORT_SYMBOL(__ocelot_write_ix);
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void __ocelot_rmw_ix(struct ocelot *ocelot, u32 val, u32 mask, u32 reg,
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u32 offset)
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{
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u16 target = reg >> TARGET_OFFSET;
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WARN_ON(!target);
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regmap_update_bits(ocelot->targets[target],
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ocelot->map[target][reg & REG_MASK] + offset,
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mask, val);
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}
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EXPORT_SYMBOL(__ocelot_rmw_ix);
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u32 ocelot_port_readl(struct ocelot_port *port, u32 reg)
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{
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return readl(port->regs + reg);
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}
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EXPORT_SYMBOL(ocelot_port_readl);
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void ocelot_port_writel(struct ocelot_port *port, u32 val, u32 reg)
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{
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writel(val, port->regs + reg);
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}
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EXPORT_SYMBOL(ocelot_port_writel);
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int ocelot_regfields_init(struct ocelot *ocelot,
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const struct reg_field *const regfields)
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{
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unsigned int i;
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u16 target;
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for (i = 0; i < REGFIELD_MAX; i++) {
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struct reg_field regfield = {};
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u32 reg = regfields[i].reg;
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if (!reg)
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continue;
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target = regfields[i].reg >> TARGET_OFFSET;
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regfield.reg = ocelot->map[target][reg & REG_MASK];
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regfield.lsb = regfields[i].lsb;
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regfield.msb = regfields[i].msb;
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ocelot->regfields[i] =
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devm_regmap_field_alloc(ocelot->dev,
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ocelot->targets[target],
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regfield);
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if (IS_ERR(ocelot->regfields[i]))
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return PTR_ERR(ocelot->regfields[i]);
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}
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return 0;
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}
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EXPORT_SYMBOL(ocelot_regfields_init);
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static struct regmap_config ocelot_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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};
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struct regmap *ocelot_io_platform_init(struct ocelot *ocelot,
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struct platform_device *pdev,
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const char *name)
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{
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struct resource *res;
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void __iomem *regs;
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
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regs = devm_ioremap_resource(ocelot->dev, res);
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if (IS_ERR(regs))
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return ERR_CAST(regs);
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ocelot_regmap_config.name = name;
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return devm_regmap_init_mmio(ocelot->dev, regs,
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&ocelot_regmap_config);
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}
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EXPORT_SYMBOL(ocelot_io_platform_init);
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