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3306657119
To fit with latest rtc driver updates, rtc st,syscfg property must contain the control register offset of pwrcfg and the mask corresponding to the DBP (Disable Backup Protection) bit. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
715 lines
17 KiB
Plaintext
715 lines
17 KiB
Plaintext
/*
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* Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public
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* License along with this file; if not, write to the Free
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* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "skeleton.dtsi"
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#include "armv7-m.dtsi"
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#include <dt-bindings/clock/stm32fx-clock.h>
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#include <dt-bindings/mfd/stm32f4-rcc.h>
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/ {
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32000>;
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};
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clk_i2s_ckin: i2s-ckin {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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};
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soc {
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timer2: timer@40000000 {
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compatible = "st,stm32-timer";
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reg = <0x40000000 0x400>;
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interrupts = <28>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
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status = "disabled";
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};
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timers2: timers@40000000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40000000 0x400>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@1 {
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compatible = "st,stm32-timer-trigger";
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reg = <1>;
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status = "disabled";
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};
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};
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timer3: timer@40000400 {
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compatible = "st,stm32-timer";
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reg = <0x40000400 0x400>;
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interrupts = <29>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
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status = "disabled";
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};
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timers3: timers@40000400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40000400 0x400>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@2 {
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compatible = "st,stm32-timer-trigger";
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reg = <2>;
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status = "disabled";
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};
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};
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timer4: timer@40000800 {
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compatible = "st,stm32-timer";
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reg = <0x40000800 0x400>;
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interrupts = <30>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
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status = "disabled";
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};
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timers4: timers@40000800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40000800 0x400>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@3 {
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compatible = "st,stm32-timer-trigger";
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reg = <3>;
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status = "disabled";
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};
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};
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timer5: timer@40000c00 {
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compatible = "st,stm32-timer";
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reg = <0x40000c00 0x400>;
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interrupts = <50>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
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};
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timers5: timers@40000c00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40000C00 0x400>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@4 {
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compatible = "st,stm32-timer-trigger";
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reg = <4>;
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status = "disabled";
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};
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};
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timer6: timer@40001000 {
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compatible = "st,stm32-timer";
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reg = <0x40001000 0x400>;
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interrupts = <54>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
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status = "disabled";
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};
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timers6: timers@40001000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40001000 0x400>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
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clock-names = "int";
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status = "disabled";
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timer@5 {
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compatible = "st,stm32-timer-trigger";
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reg = <5>;
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status = "disabled";
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};
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};
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timer7: timer@40001400 {
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compatible = "st,stm32-timer";
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reg = <0x40001400 0x400>;
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interrupts = <55>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
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status = "disabled";
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};
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timers7: timers@40001400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40001400 0x400>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
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clock-names = "int";
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status = "disabled";
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timer@6 {
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compatible = "st,stm32-timer-trigger";
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reg = <6>;
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status = "disabled";
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};
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};
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timers12: timers@40001800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40001800 0x400>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@11 {
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compatible = "st,stm32-timer-trigger";
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reg = <11>;
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status = "disabled";
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};
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};
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timers13: timers@40001c00 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40001C00 0x400>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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};
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timers14: timers@40002000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40002000 0x400>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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};
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rtc: rtc@40002800 {
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compatible = "st,stm32-rtc";
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reg = <0x40002800 0x400>;
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clocks = <&rcc 1 CLK_RTC>;
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clock-names = "ck_rtc";
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assigned-clocks = <&rcc 1 CLK_RTC>;
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assigned-clock-parents = <&rcc 1 CLK_LSE>;
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interrupt-parent = <&exti>;
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interrupts = <17 1>;
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interrupt-names = "alarm";
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st,syscfg = <&pwrcfg 0x00 0x100>;
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status = "disabled";
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};
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iwdg: watchdog@40003000 {
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compatible = "st,stm32-iwdg";
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reg = <0x40003000 0x400>;
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clocks = <&clk_lsi>;
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status = "disabled";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-uart";
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reg = <0x40004400 0x400>;
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interrupts = <38>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
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status = "disabled";
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};
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usart3: serial@40004800 {
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compatible = "st,stm32-uart";
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reg = <0x40004800 0x400>;
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interrupts = <39>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
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status = "disabled";
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dmas = <&dma1 1 4 0x400 0x0>,
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<&dma1 3 4 0x400 0x0>;
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dma-names = "rx", "tx";
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};
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usart4: serial@40004c00 {
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compatible = "st,stm32-uart";
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reg = <0x40004c00 0x400>;
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interrupts = <52>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
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status = "disabled";
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};
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usart5: serial@40005000 {
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compatible = "st,stm32-uart";
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reg = <0x40005000 0x400>;
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interrupts = <53>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
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status = "disabled";
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};
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i2c1: i2c@40005400 {
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compatible = "st,stm32f4-i2c";
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reg = <0x40005400 0x400>;
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interrupts = <31>,
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<32>;
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resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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dac: dac@40007400 {
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compatible = "st,stm32f4-dac-core";
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reg = <0x40007400 0x400>;
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resets = <&rcc STM32F4_APB1_RESET(DAC)>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
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clock-names = "pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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dac1: dac@1 {
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compatible = "st,stm32-dac";
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#io-channels-cells = <1>;
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reg = <1>;
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status = "disabled";
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};
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dac2: dac@2 {
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compatible = "st,stm32-dac";
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#io-channels-cells = <1>;
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reg = <2>;
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status = "disabled";
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};
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};
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usart7: serial@40007800 {
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compatible = "st,stm32-uart";
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reg = <0x40007800 0x400>;
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interrupts = <82>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
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status = "disabled";
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};
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usart8: serial@40007c00 {
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compatible = "st,stm32-uart";
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reg = <0x40007c00 0x400>;
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interrupts = <83>;
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clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
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status = "disabled";
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};
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timers1: timers@40010000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40010000 0x400>;
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clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@0 {
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compatible = "st,stm32-timer-trigger";
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reg = <0>;
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status = "disabled";
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};
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};
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timers8: timers@40010400 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32-timers";
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reg = <0x40010400 0x400>;
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clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
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clock-names = "int";
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status = "disabled";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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};
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timer@7 {
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compatible = "st,stm32-timer-trigger";
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reg = <7>;
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status = "disabled";
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};
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};
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usart1: serial@40011000 {
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compatible = "st,stm32-uart";
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reg = <0x40011000 0x400>;
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interrupts = <37>;
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clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
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status = "disabled";
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dmas = <&dma2 2 4 0x400 0x0>,
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<&dma2 7 4 0x400 0x0>;
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dma-names = "rx", "tx";
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};
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usart6: serial@40011400 {
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compatible = "st,stm32-uart";
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reg = <0x40011400 0x400>;
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interrupts = <71>;
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clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
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status = "disabled";
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};
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adc: adc@40012000 {
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compatible = "st,stm32f4-adc-core";
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reg = <0x40012000 0x400>;
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interrupts = <18>;
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clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
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clock-names = "adc";
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interrupt-controller;
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#interrupt-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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adc1: adc@0 {
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compatible = "st,stm32f4-adc";
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#io-channel-cells = <1>;
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reg = <0x0>;
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clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
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interrupt-parent = <&adc>;
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interrupts = <0>;
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dmas = <&dma2 0 0 0x400 0x0>;
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dma-names = "rx";
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status = "disabled";
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};
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adc2: adc@100 {
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compatible = "st,stm32f4-adc";
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#io-channel-cells = <1>;
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reg = <0x100>;
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clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
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interrupt-parent = <&adc>;
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interrupts = <1>;
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dmas = <&dma2 3 1 0x400 0x0>;
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dma-names = "rx";
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status = "disabled";
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};
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adc3: adc@200 {
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compatible = "st,stm32f4-adc";
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#io-channel-cells = <1>;
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reg = <0x200>;
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clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
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interrupt-parent = <&adc>;
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interrupts = <2>;
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dmas = <&dma2 1 2 0x400 0x0>;
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dma-names = "rx";
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status = "disabled";
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};
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};
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sdio: sdio@40012c00 {
|
|
compatible = "arm,pl180", "arm,primecell";
|
|
arm,primecell-periphid = <0x00880180>;
|
|
reg = <0x40012c00 0x400>;
|
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
|
|
clock-names = "apb_pclk";
|
|
interrupts = <49>;
|
|
max-frequency = <48000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
syscfg: system-config@40013800 {
|
|
compatible = "syscon";
|
|
reg = <0x40013800 0x400>;
|
|
};
|
|
|
|
exti: interrupt-controller@40013c00 {
|
|
compatible = "st,stm32-exti";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
reg = <0x40013C00 0x400>;
|
|
interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
|
|
};
|
|
|
|
timers9: timers@40014000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40014000 0x400>;
|
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
|
|
timer@8 {
|
|
compatible = "st,stm32-timer-trigger";
|
|
reg = <8>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers10: timers@40014400 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40014400 0x400>;
|
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
timers11: timers@40014800 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32-timers";
|
|
reg = <0x40014800 0x400>;
|
|
clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
|
|
clock-names = "int";
|
|
status = "disabled";
|
|
|
|
pwm {
|
|
compatible = "st,stm32-pwm";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
pwrcfg: power-config@40007000 {
|
|
compatible = "syscon";
|
|
reg = <0x40007000 0x400>;
|
|
};
|
|
|
|
ltdc: display-controller@40016800 {
|
|
compatible = "st,stm32-ltdc";
|
|
reg = <0x40016800 0x200>;
|
|
interrupts = <88>, <89>;
|
|
resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
|
|
clocks = <&rcc 1 CLK_LCD>;
|
|
clock-names = "lcd";
|
|
status = "disabled";
|
|
};
|
|
|
|
crc: crc@40023000 {
|
|
compatible = "st,stm32f4-crc";
|
|
reg = <0x40023000 0x400>;
|
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rcc: rcc@40023810 {
|
|
#reset-cells = <1>;
|
|
#clock-cells = <2>;
|
|
compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
|
|
reg = <0x40023800 0x400>;
|
|
clocks = <&clk_hse>, <&clk_i2s_ckin>;
|
|
st,syscfg = <&pwrcfg>;
|
|
assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
|
|
assigned-clock-rates = <1000000>;
|
|
};
|
|
|
|
dma1: dma-controller@40026000 {
|
|
compatible = "st,stm32-dma";
|
|
reg = <0x40026000 0x400>;
|
|
interrupts = <11>,
|
|
<12>,
|
|
<13>,
|
|
<14>,
|
|
<15>,
|
|
<16>,
|
|
<17>,
|
|
<47>;
|
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
|
|
#dma-cells = <4>;
|
|
};
|
|
|
|
dma2: dma-controller@40026400 {
|
|
compatible = "st,stm32-dma";
|
|
reg = <0x40026400 0x400>;
|
|
interrupts = <56>,
|
|
<57>,
|
|
<58>,
|
|
<59>,
|
|
<60>,
|
|
<68>,
|
|
<69>,
|
|
<70>;
|
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
|
|
#dma-cells = <4>;
|
|
st,mem2mem;
|
|
};
|
|
|
|
mac: ethernet@40028000 {
|
|
compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
|
|
reg = <0x40028000 0x8000>;
|
|
reg-names = "stmmaceth";
|
|
interrupts = <61>;
|
|
interrupt-names = "macirq";
|
|
clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
|
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
|
|
<&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
|
|
<&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
|
|
st,syscon = <&syscfg 0x4>;
|
|
snps,pbl = <8>;
|
|
snps,mixed-burst;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbotg_hs: usb@40040000 {
|
|
compatible = "snps,dwc2";
|
|
reg = <0x40040000 0x40000>;
|
|
interrupts = <77>;
|
|
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
|
|
clock-names = "otg";
|
|
status = "disabled";
|
|
};
|
|
|
|
usbotg_fs: usb@50000000 {
|
|
compatible = "st,stm32f4x9-fsotg";
|
|
reg = <0x50000000 0x40000>;
|
|
interrupts = <67>;
|
|
clocks = <&rcc 0 39>;
|
|
clock-names = "otg";
|
|
status = "disabled";
|
|
};
|
|
|
|
dcmi: dcmi@50050000 {
|
|
compatible = "st,stm32-dcmi";
|
|
reg = <0x50050000 0x400>;
|
|
interrupts = <78>;
|
|
resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
|
|
clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
|
|
clock-names = "mclk";
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&dcmi_pins>;
|
|
dmas = <&dma2 1 1 0x414 0x3>;
|
|
dma-names = "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
rng: rng@50060800 {
|
|
compatible = "st,stm32-rng";
|
|
reg = <0x50060800 0x400>;
|
|
interrupts = <80>;
|
|
clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
|
|
|
|
};
|
|
};
|
|
};
|
|
|
|
&systick {
|
|
clocks = <&rcc 1 SYSTICK>;
|
|
status = "okay";
|
|
};
|