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782de70c42
Both pgtable_cache_init() and pgd_cache_init() are used to initialize kmem cache for page table allocations on several architectures that do not use PAGE_SIZE tables for one or more levels of the page table hierarchy. Most architectures do not implement these functions and use __weak default NOP implementation of pgd_cache_init(). Since there is no such default for pgtable_cache_init(), its empty stub is duplicated among most architectures. Rename the definitions of pgd_cache_init() to pgtable_cache_init() and drop empty stubs of pgtable_cache_init(). Link: http://lkml.kernel.org/r/1566457046-22637-1-git-send-email-rppt@linux.ibm.com Signed-off-by: Mike Rapoport <rppt@linux.ibm.com> Acked-by: Will Deacon <will@kernel.org> [arm64] Acked-by: Thomas Gleixner <tglx@linutronix.de> [x86] Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Matthew Wilcox <willy@infradead.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
270 lines
7.1 KiB
C
270 lines
7.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_PGTABLE_64_H
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#define _ASM_X86_PGTABLE_64_H
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#include <linux/const.h>
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#include <asm/pgtable_64_types.h>
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#ifndef __ASSEMBLY__
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/*
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* This file contains the functions and defines necessary to modify and use
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* the x86-64 page table tree.
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*/
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#include <asm/processor.h>
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#include <linux/bitops.h>
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#include <linux/threads.h>
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#include <asm/fixmap.h>
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extern p4d_t level4_kernel_pgt[512];
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extern p4d_t level4_ident_pgt[512];
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extern pud_t level3_kernel_pgt[512];
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extern pud_t level3_ident_pgt[512];
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extern pmd_t level2_kernel_pgt[512];
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extern pmd_t level2_fixmap_pgt[512];
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extern pmd_t level2_ident_pgt[512];
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extern pte_t level1_fixmap_pgt[512 * FIXMAP_PMD_NUM];
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extern pgd_t init_top_pgt[];
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#define swapper_pg_dir init_top_pgt
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extern void paging_init(void);
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static inline void sync_initial_page_table(void) { }
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#define pte_ERROR(e) \
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pr_err("%s:%d: bad pte %p(%016lx)\n", \
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__FILE__, __LINE__, &(e), pte_val(e))
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#define pmd_ERROR(e) \
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pr_err("%s:%d: bad pmd %p(%016lx)\n", \
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__FILE__, __LINE__, &(e), pmd_val(e))
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#define pud_ERROR(e) \
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pr_err("%s:%d: bad pud %p(%016lx)\n", \
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__FILE__, __LINE__, &(e), pud_val(e))
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#if CONFIG_PGTABLE_LEVELS >= 5
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#define p4d_ERROR(e) \
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pr_err("%s:%d: bad p4d %p(%016lx)\n", \
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__FILE__, __LINE__, &(e), p4d_val(e))
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#endif
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#define pgd_ERROR(e) \
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pr_err("%s:%d: bad pgd %p(%016lx)\n", \
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__FILE__, __LINE__, &(e), pgd_val(e))
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struct mm_struct;
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void set_pte_vaddr_p4d(p4d_t *p4d_page, unsigned long vaddr, pte_t new_pte);
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void set_pte_vaddr_pud(pud_t *pud_page, unsigned long vaddr, pte_t new_pte);
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static inline void native_set_pte(pte_t *ptep, pte_t pte)
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{
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WRITE_ONCE(*ptep, pte);
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}
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static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep)
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{
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native_set_pte(ptep, native_make_pte(0));
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}
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static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
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{
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native_set_pte(ptep, pte);
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}
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static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
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{
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WRITE_ONCE(*pmdp, pmd);
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}
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static inline void native_pmd_clear(pmd_t *pmd)
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{
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native_set_pmd(pmd, native_make_pmd(0));
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}
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static inline pte_t native_ptep_get_and_clear(pte_t *xp)
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{
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#ifdef CONFIG_SMP
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return native_make_pte(xchg(&xp->pte, 0));
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#else
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/* native_local_ptep_get_and_clear,
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but duplicated because of cyclic dependency */
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pte_t ret = *xp;
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native_pte_clear(NULL, 0, xp);
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return ret;
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#endif
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}
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static inline pmd_t native_pmdp_get_and_clear(pmd_t *xp)
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{
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#ifdef CONFIG_SMP
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return native_make_pmd(xchg(&xp->pmd, 0));
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#else
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/* native_local_pmdp_get_and_clear,
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but duplicated because of cyclic dependency */
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pmd_t ret = *xp;
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native_pmd_clear(xp);
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return ret;
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#endif
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}
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static inline void native_set_pud(pud_t *pudp, pud_t pud)
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{
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WRITE_ONCE(*pudp, pud);
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}
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static inline void native_pud_clear(pud_t *pud)
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{
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native_set_pud(pud, native_make_pud(0));
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}
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static inline pud_t native_pudp_get_and_clear(pud_t *xp)
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{
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#ifdef CONFIG_SMP
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return native_make_pud(xchg(&xp->pud, 0));
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#else
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/* native_local_pudp_get_and_clear,
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* but duplicated because of cyclic dependency
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*/
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pud_t ret = *xp;
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native_pud_clear(xp);
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return ret;
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#endif
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}
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static inline void native_set_p4d(p4d_t *p4dp, p4d_t p4d)
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{
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pgd_t pgd;
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if (pgtable_l5_enabled() || !IS_ENABLED(CONFIG_PAGE_TABLE_ISOLATION)) {
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WRITE_ONCE(*p4dp, p4d);
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return;
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}
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pgd = native_make_pgd(native_p4d_val(p4d));
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pgd = pti_set_user_pgtbl((pgd_t *)p4dp, pgd);
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WRITE_ONCE(*p4dp, native_make_p4d(native_pgd_val(pgd)));
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}
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static inline void native_p4d_clear(p4d_t *p4d)
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{
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native_set_p4d(p4d, native_make_p4d(0));
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}
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static inline void native_set_pgd(pgd_t *pgdp, pgd_t pgd)
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{
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WRITE_ONCE(*pgdp, pti_set_user_pgtbl(pgdp, pgd));
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}
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static inline void native_pgd_clear(pgd_t *pgd)
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{
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native_set_pgd(pgd, native_make_pgd(0));
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}
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extern void sync_global_pgds(unsigned long start, unsigned long end);
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/*
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* Conversion functions: convert a page and protection to a page entry,
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* and a page entry and page directory to the page they refer to.
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*/
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/*
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* Level 4 access.
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*/
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#define mk_kernel_pgd(address) __pgd((address) | _KERNPG_TABLE)
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/* PUD - Level3 access */
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/* PMD - Level 2 access */
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/* PTE - Level 1 access. */
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/* x86-64 always has all page tables mapped. */
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#define pte_offset_map(dir, address) pte_offset_kernel((dir), (address))
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#define pte_unmap(pte) ((void)(pte))/* NOP */
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/*
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* Encode and de-code a swap entry
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*
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* | ... | 11| 10| 9|8|7|6|5| 4| 3|2| 1|0| <- bit number
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* | ... |SW3|SW2|SW1|G|L|D|A|CD|WT|U| W|P| <- bit names
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* | TYPE (59-63) | ~OFFSET (9-58) |0|0|X|X| X| X|X|SD|0| <- swp entry
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*
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* G (8) is aliased and used as a PROT_NONE indicator for
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* !present ptes. We need to start storing swap entries above
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* there. We also need to avoid using A and D because of an
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* erratum where they can be incorrectly set by hardware on
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* non-present PTEs.
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*
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* SD (1) in swp entry is used to store soft dirty bit, which helps us
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* remember soft dirty over page migration
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*
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* Bit 7 in swp entry should be 0 because pmd_present checks not only P,
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* but also L and G.
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*
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* The offset is inverted by a binary not operation to make the high
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* physical bits set.
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*/
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#define SWP_TYPE_BITS 5
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#define SWP_OFFSET_FIRST_BIT (_PAGE_BIT_PROTNONE + 1)
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/* We always extract/encode the offset by shifting it all the way up, and then down again */
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#define SWP_OFFSET_SHIFT (SWP_OFFSET_FIRST_BIT+SWP_TYPE_BITS)
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#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS)
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/* Extract the high bits for type */
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#define __swp_type(x) ((x).val >> (64 - SWP_TYPE_BITS))
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/* Shift up (to get rid of type), then down to get value */
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#define __swp_offset(x) (~(x).val << SWP_TYPE_BITS >> SWP_OFFSET_SHIFT)
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/*
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* Shift the offset up "too far" by TYPE bits, then down again
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* The offset is inverted by a binary not operation to make the high
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* physical bits set.
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*/
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#define __swp_entry(type, offset) ((swp_entry_t) { \
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(~(unsigned long)(offset) << SWP_OFFSET_SHIFT >> SWP_TYPE_BITS) \
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| ((unsigned long)(type) << (64-SWP_TYPE_BITS)) })
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#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val((pte)) })
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#define __pmd_to_swp_entry(pmd) ((swp_entry_t) { pmd_val((pmd)) })
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#define __swp_entry_to_pte(x) ((pte_t) { .pte = (x).val })
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#define __swp_entry_to_pmd(x) ((pmd_t) { .pmd = (x).val })
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extern int kern_addr_valid(unsigned long addr);
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extern void cleanup_highmap(void);
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#define HAVE_ARCH_UNMAPPED_AREA
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#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
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#define PAGE_AGP PAGE_KERNEL_NOCACHE
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#define HAVE_PAGE_AGP 1
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/* fs/proc/kcore.c */
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#define kc_vaddr_to_offset(v) ((v) & __VIRTUAL_MASK)
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#define kc_offset_to_vaddr(o) ((o) | ~__VIRTUAL_MASK)
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#define __HAVE_ARCH_PTE_SAME
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#define vmemmap ((struct page *)VMEMMAP_START)
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extern void init_extra_mapping_uc(unsigned long phys, unsigned long size);
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extern void init_extra_mapping_wb(unsigned long phys, unsigned long size);
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#define gup_fast_permitted gup_fast_permitted
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static inline bool gup_fast_permitted(unsigned long start, unsigned long end)
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{
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if (end >> __VIRTUAL_MASK_SHIFT)
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return false;
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return true;
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}
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#include <asm/pgtable-invert.h>
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_X86_PGTABLE_64_H */
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