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NVIDIA's Tegra has multiple UART controller which supports: - APB DMA based controller fifo read/write. - End Of Data interrupt in incoming data to know whether end of frame achieve or not. - HW controlled RTS and CTS flow control to reduce SW overhead. Add serial driver to use all above feature. Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Alan Cox <alan@linux.intel.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
25 lines
826 B
Plaintext
25 lines
826 B
Plaintext
NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver.
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Required properties:
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- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
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- reg: Should contain UART controller registers location and length.
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- interrupts: Should contain UART controller interrupts.
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- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
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request selector for this UART controller.
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Optional properties:
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- nvidia,enable-modem-interrupt: Enable modem interrupts. Should be enable
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only if all 8 lines of UART controller are pinmuxed.
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Example:
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serial@70006000 {
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compatible = "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart";
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reg = <0x70006000 0x40>;
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reg-shift = <2>;
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interrupts = <0 36 0x04>;
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nvidia,dma-request-selector = <&apbdma 8>;
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nvidia,enable-modem-interrupt;
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status = "disabled";
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};
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