linux_dsm_epyc7002/arch/x86/kernel/cpu
Borislav Petkov 328935e634 Revert "x86, AMD: Fix APIC timer erratum 400 affecting K8 Rev.A-E processors"
This reverts commit e20a2d205c, as it crashes
certain boxes with specific AMD CPU models.

Moving the lower endpoint of the Erratum 400 check to accomodate
earlier K8 revisions (A-E) opens a can of worms which is simply
not worth to fix properly by tweaking the errata checking
framework:

* missing IntPenging MSR on revisions < CG cause #GP:

http://marc.info/?l=linux-kernel&m=130541471818831

* makes earlier revisions use the LAPIC timer instead of the C1E
idle routine which switches to HPET, thus not waking up in
deeper C-states:

http://lkml.org/lkml/2011/4/24/20

Therefore, leave the original boundary starting with K8-revF.

Signed-off-by: Ingo Molnar <mingo@elte.hu>
2011-05-17 15:28:33 +02:00
..
cpufreq Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip 2011-03-18 10:45:21 -07:00
mcheck x86, apic: Fix spurious error interrupts triggering on all non-boot APs 2011-05-16 13:48:25 +02:00
mtrr x86, mtrr, pat: Fix one cpu getting out of sync during resume 2011-03-29 16:17:42 -07:00
.gitignore
amd.c Revert "x86, AMD: Fix APIC timer erratum 400 affecting K8 Rev.A-E processors" 2011-05-17 15:28:33 +02:00
bugs_64.c
bugs.c
centaur.c
common.c Merge branch 'x86-mm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip 2011-03-15 19:49:10 -07:00
cpu.h
cyrix.c
hypervisor.c
intel_cacheinfo.c Merge branch 'x86-mm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip 2011-03-15 19:49:10 -07:00
intel.c x86: Unify CPU -> NUMA node mapping between 32 and 64bit 2011-01-28 14:54:09 +01:00
Makefile
mkcapflags.pl
mshyperv.c
perf_event_amd.c perf, x86: Fix AMD family 15h FPU event constraints 2011-04-19 10:07:55 +02:00
perf_event_intel_ds.c perf, x86: Use INTEL_*_CONSTRAINT() for all PEBS event constraints 2011-03-16 14:04:12 +01:00
perf_event_intel_lbr.c
perf_event_intel.c perf events, x86: Fix Intel Nehalem and Westmere last level cache event definitions 2011-05-06 11:24:48 +02:00
perf_event_p4.c perf, x86, nmi: Move LVT un-masking into irq handlers 2011-04-27 17:59:11 +02:00
perf_event_p6.c perf, x86: Store perfctr msr addresses in config_base/event_base 2011-02-16 13:30:52 +01:00
perf_event.c perf, x86, nmi: Move LVT un-masking into irq handlers 2011-04-27 17:59:11 +02:00
perfctr-watchdog.c perf, x86: Add new AMD family 15h msrs to perfctr reservation code 2011-02-16 13:30:50 +01:00
powerflags.c
proc.c
scattered.c
sched.c
topology.c
transmeta.c
umc.c
vmware.c x86: Fix common misspellings 2011-03-18 10:39:30 +01:00