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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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79ffac8599
In the current scheme, on submitting a request we take a single global GEM wakeref, which trickles down to wake up all GT power domains. This is undesirable as we would like to be able to localise our power management to the available power domains and to remove the global GEM operations from the heart of the driver. (The intent there is to push global GEM decisions to the boundary as used by the GEM user interface.) Now during request construction, each request is responsible via its logical context to acquire a wakeref on each power domain it intends to utilize. Currently, each request takes a wakeref on the engine(s) and the engines themselves take a chipset wakeref. This gives us a transition on each engine which we can extend if we want to insert more powermangement control (such as soft rc6). The global GEM operations that currently require a struct_mutex are reduced to listening to pm events from the chipset GT wakeref. As we reduce the struct_mutex requirement, these listeners should evaporate. Perhaps the biggest immediate change is that this removes the struct_mutex requirement around GT power management, allowing us greater flexibility in request construction. Another important knock-on effect, is that by tracking engine usage, we can insert a switch back to the kernel context on that engine immediately, avoiding any extra delay or inserting global synchronisation barriers. This makes tracking when an engine and its associated contexts are idle much easier -- important for when we forgo our assumed execution ordering and need idle barriers to unpin used contexts. In the process, it means we remove a large chunk of code whose only purpose was to switch back to the kernel context. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Imre Deak <imre.deak@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190424200717.1686-5-chris@chris-wilson.co.uk
69 lines
1.8 KiB
C
69 lines
1.8 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2008-2018 Intel Corporation
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*/
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#ifndef I915_RESET_H
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#define I915_RESET_H
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <linux/srcu.h>
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#include "gt/intel_engine_types.h"
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struct drm_i915_private;
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struct i915_request;
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struct intel_engine_cs;
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struct intel_guc;
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__printf(4, 5)
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void i915_handle_error(struct drm_i915_private *i915,
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intel_engine_mask_t engine_mask,
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unsigned long flags,
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const char *fmt, ...);
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#define I915_ERROR_CAPTURE BIT(0)
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void i915_clear_error_registers(struct drm_i915_private *i915);
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void i915_reset(struct drm_i915_private *i915,
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intel_engine_mask_t stalled_mask,
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const char *reason);
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int i915_reset_engine(struct intel_engine_cs *engine,
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const char *reason);
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void i915_reset_request(struct i915_request *rq, bool guilty);
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int __must_check i915_reset_trylock(struct drm_i915_private *i915);
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void i915_reset_unlock(struct drm_i915_private *i915, int tag);
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int i915_terminally_wedged(struct drm_i915_private *i915);
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bool intel_has_gpu_reset(struct drm_i915_private *i915);
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bool intel_has_reset_engine(struct drm_i915_private *i915);
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int intel_gpu_reset(struct drm_i915_private *i915,
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intel_engine_mask_t engine_mask);
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int intel_reset_guc(struct drm_i915_private *i915);
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struct i915_wedge_me {
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struct delayed_work work;
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struct drm_i915_private *i915;
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const char *name;
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};
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void __i915_init_wedge(struct i915_wedge_me *w,
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struct drm_i915_private *i915,
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long timeout,
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const char *name);
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void __i915_fini_wedge(struct i915_wedge_me *w);
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#define i915_wedge_on_timeout(W, DEV, TIMEOUT) \
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for (__i915_init_wedge((W), (DEV), (TIMEOUT), __func__); \
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(W)->i915; \
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__i915_fini_wedge((W)))
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#endif /* I915_RESET_H */
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