mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 20:53:00 +07:00
d680ebed91
Increase limit of max CQE from 8K to 32K to allow demanding
applications to work over SoftRoCE with same configuration
as most RoCEv2 HW vendors have.
Fixes: 8700e3e7c4 ("Soft RoCE driver")
Signed-off-by: Yonatan Cohen <yonatanc@mellanox.com>
Reviewed-by: Moni Shoua <monis@mellanox.com>
Signed-off-by: Leon Romanovsky <leon@kernel.org>
Signed-off-by: Doug Ledford <dledford@redhat.com>
173 lines
4.8 KiB
C
173 lines
4.8 KiB
C
/*
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* Copyright (c) 2016 Mellanox Technologies Ltd. All rights reserved.
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* Copyright (c) 2015 System Fabric Works, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef RXE_PARAM_H
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#define RXE_PARAM_H
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static inline enum ib_mtu rxe_mtu_int_to_enum(int mtu)
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{
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if (mtu < 256)
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return 0;
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else if (mtu < 512)
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return IB_MTU_256;
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else if (mtu < 1024)
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return IB_MTU_512;
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else if (mtu < 2048)
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return IB_MTU_1024;
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else if (mtu < 4096)
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return IB_MTU_2048;
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else
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return IB_MTU_4096;
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}
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/* Find the IB mtu for a given network MTU. */
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static inline enum ib_mtu eth_mtu_int_to_enum(int mtu)
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{
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mtu -= RXE_MAX_HDR_LENGTH;
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return rxe_mtu_int_to_enum(mtu);
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}
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/* default/initial rxe device parameter settings */
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enum rxe_device_param {
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RXE_FW_VER = 0,
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RXE_MAX_MR_SIZE = -1ull,
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RXE_PAGE_SIZE_CAP = 0xfffff000,
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RXE_VENDOR_ID = 0,
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RXE_VENDOR_PART_ID = 0,
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RXE_HW_VER = 0,
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RXE_MAX_QP = 0x10000,
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RXE_MAX_QP_WR = 0x4000,
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RXE_MAX_INLINE_DATA = 400,
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RXE_DEVICE_CAP_FLAGS = IB_DEVICE_BAD_PKEY_CNTR
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| IB_DEVICE_BAD_QKEY_CNTR
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| IB_DEVICE_AUTO_PATH_MIG
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| IB_DEVICE_CHANGE_PHY_PORT
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| IB_DEVICE_UD_AV_PORT_ENFORCE
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| IB_DEVICE_PORT_ACTIVE_EVENT
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| IB_DEVICE_SYS_IMAGE_GUID
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| IB_DEVICE_RC_RNR_NAK_GEN
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| IB_DEVICE_SRQ_RESIZE
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| IB_DEVICE_MEM_MGT_EXTENSIONS,
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RXE_MAX_SGE = 32,
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RXE_MAX_SGE_RD = 32,
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RXE_MAX_CQ = 16384,
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RXE_MAX_LOG_CQE = 15,
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RXE_MAX_MR = 2 * 1024,
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RXE_MAX_PD = 0x7ffc,
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RXE_MAX_QP_RD_ATOM = 128,
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RXE_MAX_EE_RD_ATOM = 0,
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RXE_MAX_RES_RD_ATOM = 0x3f000,
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RXE_MAX_QP_INIT_RD_ATOM = 128,
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RXE_MAX_EE_INIT_RD_ATOM = 0,
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RXE_ATOMIC_CAP = 1,
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RXE_MAX_EE = 0,
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RXE_MAX_RDD = 0,
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RXE_MAX_MW = 0,
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RXE_MAX_RAW_IPV6_QP = 0,
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RXE_MAX_RAW_ETHY_QP = 0,
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RXE_MAX_MCAST_GRP = 8192,
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RXE_MAX_MCAST_QP_ATTACH = 56,
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RXE_MAX_TOT_MCAST_QP_ATTACH = 0x70000,
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RXE_MAX_AH = 100,
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RXE_MAX_FMR = 0,
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RXE_MAX_MAP_PER_FMR = 0,
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RXE_MAX_SRQ = 960,
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RXE_MAX_SRQ_WR = 0x4000,
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RXE_MIN_SRQ_WR = 1,
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RXE_MAX_SRQ_SGE = 27,
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RXE_MIN_SRQ_SGE = 1,
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RXE_MAX_FMR_PAGE_LIST_LEN = 512,
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RXE_MAX_PKEYS = 64,
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RXE_LOCAL_CA_ACK_DELAY = 15,
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RXE_MAX_UCONTEXT = 512,
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RXE_NUM_PORT = 1,
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RXE_NUM_COMP_VECTORS = 1,
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RXE_MIN_QP_INDEX = 16,
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RXE_MAX_QP_INDEX = 0x00020000,
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RXE_MIN_SRQ_INDEX = 0x00020001,
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RXE_MAX_SRQ_INDEX = 0x00040000,
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RXE_MIN_MR_INDEX = 0x00000001,
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RXE_MAX_MR_INDEX = 0x00040000,
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RXE_MIN_MW_INDEX = 0x00040001,
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RXE_MAX_MW_INDEX = 0x00060000,
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RXE_MAX_PKT_PER_ACK = 64,
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RXE_MAX_UNACKED_PSNS = 128,
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/* Max inflight SKBs per queue pair */
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RXE_INFLIGHT_SKBS_PER_QP_HIGH = 64,
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RXE_INFLIGHT_SKBS_PER_QP_LOW = 16,
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/* Delay before calling arbiter timer */
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RXE_NSEC_ARB_TIMER_DELAY = 200,
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};
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/* default/initial rxe port parameters */
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enum rxe_port_param {
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RXE_PORT_STATE = IB_PORT_DOWN,
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RXE_PORT_MAX_MTU = IB_MTU_4096,
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RXE_PORT_ACTIVE_MTU = IB_MTU_256,
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RXE_PORT_GID_TBL_LEN = 1024,
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RXE_PORT_PORT_CAP_FLAGS = RDMA_CORE_CAP_PROT_ROCE_UDP_ENCAP,
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RXE_PORT_MAX_MSG_SZ = 0x800000,
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RXE_PORT_BAD_PKEY_CNTR = 0,
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RXE_PORT_QKEY_VIOL_CNTR = 0,
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RXE_PORT_LID = 0,
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RXE_PORT_SM_LID = 0,
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RXE_PORT_SM_SL = 0,
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RXE_PORT_LMC = 0,
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RXE_PORT_MAX_VL_NUM = 1,
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RXE_PORT_SUBNET_TIMEOUT = 0,
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RXE_PORT_INIT_TYPE_REPLY = 0,
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RXE_PORT_ACTIVE_WIDTH = IB_WIDTH_1X,
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RXE_PORT_ACTIVE_SPEED = 1,
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RXE_PORT_PKEY_TBL_LEN = 64,
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RXE_PORT_PHYS_STATE = 2,
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RXE_PORT_SUBNET_PREFIX = 0xfe80000000000000ULL,
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};
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/* default/initial port info parameters */
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enum rxe_port_info_param {
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RXE_PORT_INFO_VL_CAP = 4, /* 1-8 */
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RXE_PORT_INFO_MTU_CAP = 5, /* 4096 */
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RXE_PORT_INFO_OPER_VL = 1, /* 1 */
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};
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#endif /* RXE_PARAM_H */
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