mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 22:55:11 +07:00
3207426925
The entry order of the TSS.IST array and the order of the stack storage/mapping are not required to be the same. With the upcoming split of the debug stack this is going to fall apart as the number of TSS.IST array entries stays the same while the actual stacks are increasing. Make them separate so that code like dumpstack can just utilize the mapping order. The IST index is solely required for the actual TSS.IST array initialization. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: Andy Lutomirski <luto@kernel.org> Cc: Baoquan He <bhe@redhat.com> Cc: "Chang S. Bae" <chang.seok.bae@intel.com> Cc: Dominik Brodowski <linux@dominikbrodowski.net> Cc: Dou Liyang <douly.fnst@cn.fujitsu.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jann Horn <jannh@google.com> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Kees Cook <keescook@chromium.org> Cc: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com> Cc: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> Cc: Nicolai Stange <nstange@suse.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Qian Cai <cai@lca.pw> Cc: Sean Christopherson <sean.j.christopherson@intel.com> Cc: x86-ml <x86@kernel.org> Link: https://lkml.kernel.org/r/20190414160145.241588113@linutronix.de |
||
---|---|---|
.. | ||
mce | ||
microcode | ||
mtrr | ||
resctrl | ||
.gitignore | ||
amd.c | ||
aperfmperf.c | ||
bugs.c | ||
cacheinfo.c | ||
centaur.c | ||
common.c | ||
cpu.h | ||
cpuid-deps.c | ||
cyrix.c | ||
hygon.c | ||
hypervisor.c | ||
intel_pconfig.c | ||
intel.c | ||
Makefile | ||
match.c | ||
mkcapflags.sh | ||
mshyperv.c | ||
perfctr-watchdog.c | ||
powerflags.c | ||
proc.c | ||
rdrand.c | ||
scattered.c | ||
topology.c | ||
transmeta.c | ||
umc.c | ||
vmware.c |