mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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246ce3b675
This patch is against each libata driver. Two IRQ calls are added in ata_port_operations. - irq_on() is used to enable interrupts. - irq_ack() is used to acknowledge a device interrupt. In most drivers, ata_irq_on() and ata_irq_ack() are used for irq_on and irq_ack respectively. In some drivers (ex: ahci, sata_sil24) which cannot use them as is, ata_dummy_irq_on() and ata_dummy_irq_ack() are used. Signed-off-by: Kou Ishizaki <kou.ishizaki@toshiba.co.jp> Signed-off-by: Akira Iguchi <akira2.iguchi@toshiba.co.jp> Signed-off-by: Jeff Garzik <jeff@garzik.org>
521 lines
15 KiB
C
521 lines
15 KiB
C
/*
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* sata_svw.c - ServerWorks / Apple K2 SATA
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*
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* Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
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* Jeff Garzik <jgarzik@pobox.com>
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* Please ALWAYS copy linux-ide@vger.kernel.org
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* on emails.
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*
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* Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
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*
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* Bits from Jeff Garzik, Copyright RedHat, Inc.
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*
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* This driver probably works with non-Apple versions of the
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* Broadcom chipset...
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* libata documentation is available via 'make {ps|pdf}docs',
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* as Documentation/DocBook/libata.*
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*
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* Hardware documentation available under NDA.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#ifdef CONFIG_PPC_OF
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#endif /* CONFIG_PPC_OF */
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#define DRV_NAME "sata_svw"
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#define DRV_VERSION "2.0"
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enum {
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K2_FLAG_NO_ATAPI_DMA = (1 << 29),
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/* Taskfile registers offsets */
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K2_SATA_TF_CMD_OFFSET = 0x00,
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K2_SATA_TF_DATA_OFFSET = 0x00,
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K2_SATA_TF_ERROR_OFFSET = 0x04,
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K2_SATA_TF_NSECT_OFFSET = 0x08,
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K2_SATA_TF_LBAL_OFFSET = 0x0c,
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K2_SATA_TF_LBAM_OFFSET = 0x10,
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K2_SATA_TF_LBAH_OFFSET = 0x14,
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K2_SATA_TF_DEVICE_OFFSET = 0x18,
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K2_SATA_TF_CMDSTAT_OFFSET = 0x1c,
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K2_SATA_TF_CTL_OFFSET = 0x20,
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/* DMA base */
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K2_SATA_DMA_CMD_OFFSET = 0x30,
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/* SCRs base */
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K2_SATA_SCR_STATUS_OFFSET = 0x40,
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K2_SATA_SCR_ERROR_OFFSET = 0x44,
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K2_SATA_SCR_CONTROL_OFFSET = 0x48,
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/* Others */
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K2_SATA_SICR1_OFFSET = 0x80,
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K2_SATA_SICR2_OFFSET = 0x84,
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K2_SATA_SIM_OFFSET = 0x88,
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/* Port stride */
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K2_SATA_PORT_OFFSET = 0x100,
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board_svw4 = 0,
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board_svw8 = 1,
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};
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static const struct k2_board_info {
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unsigned int n_ports;
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unsigned long port_flags;
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} k2_board_info[] = {
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/* board_svw4 */
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{ 4, K2_FLAG_NO_ATAPI_DMA },
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/* board_svw8 */
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{ 8, K2_FLAG_NO_ATAPI_DMA },
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};
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static u8 k2_stat_check_status(struct ata_port *ap);
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static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
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{
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if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
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return -1; /* ATAPI DMA not supported */
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return 0;
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}
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static u32 k2_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
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{
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if (sc_reg > SCR_CONTROL)
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return 0xffffffffU;
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return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
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}
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static void k2_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
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u32 val)
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{
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if (sc_reg > SCR_CONTROL)
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return;
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writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
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}
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static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
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{
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struct ata_ioports *ioaddr = &ap->ioaddr;
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unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
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if (tf->ctl != ap->last_ctl) {
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writeb(tf->ctl, ioaddr->ctl_addr);
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ap->last_ctl = tf->ctl;
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ata_wait_idle(ap);
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}
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if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
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writew(tf->feature | (((u16)tf->hob_feature) << 8),
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ioaddr->feature_addr);
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writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
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ioaddr->nsect_addr);
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writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
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ioaddr->lbal_addr);
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writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
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ioaddr->lbam_addr);
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writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
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ioaddr->lbah_addr);
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} else if (is_addr) {
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writew(tf->feature, ioaddr->feature_addr);
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writew(tf->nsect, ioaddr->nsect_addr);
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writew(tf->lbal, ioaddr->lbal_addr);
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writew(tf->lbam, ioaddr->lbam_addr);
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writew(tf->lbah, ioaddr->lbah_addr);
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}
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if (tf->flags & ATA_TFLAG_DEVICE)
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writeb(tf->device, ioaddr->device_addr);
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ata_wait_idle(ap);
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}
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static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
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{
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struct ata_ioports *ioaddr = &ap->ioaddr;
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u16 nsect, lbal, lbam, lbah, feature;
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tf->command = k2_stat_check_status(ap);
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tf->device = readw(ioaddr->device_addr);
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feature = readw(ioaddr->error_addr);
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nsect = readw(ioaddr->nsect_addr);
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lbal = readw(ioaddr->lbal_addr);
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lbam = readw(ioaddr->lbam_addr);
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lbah = readw(ioaddr->lbah_addr);
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tf->feature = feature;
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tf->nsect = nsect;
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tf->lbal = lbal;
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tf->lbam = lbam;
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tf->lbah = lbah;
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if (tf->flags & ATA_TFLAG_LBA48) {
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tf->hob_feature = feature >> 8;
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tf->hob_nsect = nsect >> 8;
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tf->hob_lbal = lbal >> 8;
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tf->hob_lbam = lbam >> 8;
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tf->hob_lbah = lbah >> 8;
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}
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}
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/**
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* k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
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* @qc: Info associated with this ATA transaction.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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static void k2_bmdma_setup_mmio (struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
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u8 dmactl;
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void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
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/* load PRD table addr. */
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mb(); /* make sure PRD table writes are visible to controller */
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writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
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/* specify data direction, triple-check start bit is clear */
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dmactl = readb(mmio + ATA_DMA_CMD);
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dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
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if (!rw)
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dmactl |= ATA_DMA_WR;
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writeb(dmactl, mmio + ATA_DMA_CMD);
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/* issue r/w command if this is not a ATA DMA command*/
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if (qc->tf.protocol != ATA_PROT_DMA)
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ap->ops->exec_command(ap, &qc->tf);
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}
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/**
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* k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
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* @qc: Info associated with this ATA transaction.
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*
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* LOCKING:
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* spin_lock_irqsave(host lock)
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*/
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static void k2_bmdma_start_mmio (struct ata_queued_cmd *qc)
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{
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struct ata_port *ap = qc->ap;
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void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
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u8 dmactl;
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/* start host DMA transaction */
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dmactl = readb(mmio + ATA_DMA_CMD);
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writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
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/* There is a race condition in certain SATA controllers that can
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be seen when the r/w command is given to the controller before the
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host DMA is started. On a Read command, the controller would initiate
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the command to the drive even before it sees the DMA start. When there
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are very fast drives connected to the controller, or when the data request
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hits in the drive cache, there is the possibility that the drive returns a part
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or all of the requested data to the controller before the DMA start is issued.
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In this case, the controller would become confused as to what to do with the data.
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In the worst case when all the data is returned back to the controller, the
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controller could hang. In other cases it could return partial data returning
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in data corruption. This problem has been seen in PPC systems and can also appear
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on an system with very fast disks, where the SATA controller is sitting behind a
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number of bridges, and hence there is significant latency between the r/w command
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and the start command. */
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/* issue r/w command if the access is to ATA*/
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if (qc->tf.protocol == ATA_PROT_DMA)
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ap->ops->exec_command(ap, &qc->tf);
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}
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static u8 k2_stat_check_status(struct ata_port *ap)
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{
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return readl((void __iomem *) ap->ioaddr.status_addr);
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}
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#ifdef CONFIG_PPC_OF
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/*
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* k2_sata_proc_info
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* inout : decides on the direction of the dataflow and the meaning of the
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* variables
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* buffer: If inout==FALSE data is being written to it else read from it
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* *start: If inout==FALSE start of the valid data in the buffer
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* offset: If inout==FALSE offset from the beginning of the imaginary file
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* from which we start writing into the buffer
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* length: If inout==FALSE max number of bytes to be written into the buffer
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* else number of bytes in the buffer
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*/
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static int k2_sata_proc_info(struct Scsi_Host *shost, char *page, char **start,
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off_t offset, int count, int inout)
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{
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struct ata_port *ap;
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struct device_node *np;
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int len, index;
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/* Find the ata_port */
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ap = ata_shost_to_port(shost);
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if (ap == NULL)
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return 0;
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/* Find the OF node for the PCI device proper */
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np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
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if (np == NULL)
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return 0;
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/* Match it to a port node */
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index = (ap == ap->host->ports[0]) ? 0 : 1;
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for (np = np->child; np != NULL; np = np->sibling) {
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const u32 *reg = get_property(np, "reg", NULL);
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if (!reg)
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continue;
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if (index == *reg)
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break;
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}
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if (np == NULL)
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return 0;
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len = sprintf(page, "devspec: %s\n", np->full_name);
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return len;
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}
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#endif /* CONFIG_PPC_OF */
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static struct scsi_host_template k2_sata_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.slave_destroy = ata_scsi_slave_destroy,
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#ifdef CONFIG_PPC_OF
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.proc_info = k2_sata_proc_info,
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#endif
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.bios_param = ata_std_bios_param,
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};
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static const struct ata_port_operations k2_sata_ops = {
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.port_disable = ata_port_disable,
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.tf_load = k2_sata_tf_load,
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.tf_read = k2_sata_tf_read,
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.check_status = k2_stat_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.check_atapi_dma = k2_sata_check_atapi_dma,
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.bmdma_setup = k2_bmdma_setup_mmio,
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.bmdma_start = k2_bmdma_start_mmio,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_data_xfer,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = ata_bmdma_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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.scr_read = k2_sata_scr_read,
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.scr_write = k2_sata_scr_write,
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.port_start = ata_port_start,
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};
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static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
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{
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port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
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port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
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port->feature_addr =
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port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
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port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
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port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
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port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
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port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;
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port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;
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port->command_addr =
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port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;
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port->altstatus_addr =
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port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;
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port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;
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port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;
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}
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static int k2_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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static int printed_version;
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struct device *dev = &pdev->dev;
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struct ata_probe_ent *probe_ent;
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void __iomem *mmio_base;
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const struct k2_board_info *board_info =
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&k2_board_info[ent->driver_data];
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int rc;
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int i;
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if (!printed_version++)
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dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
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/*
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* If this driver happens to only be useful on Apple's K2, then
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* we should check that here as it has a normal Serverworks ID
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*/
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rc = pcim_enable_device(pdev);
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if (rc)
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return rc;
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/*
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* Check if we have resources mapped at all (second function may
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* have been disabled by firmware)
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*/
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if (pci_resource_len(pdev, 5) == 0)
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return -ENODEV;
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/* Request and iomap PCI regions */
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rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME);
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if (rc == -EBUSY)
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pcim_pin_device(pdev);
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if (rc)
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return rc;
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rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
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if (rc)
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return rc;
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rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
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if (rc)
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return rc;
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probe_ent = devm_kzalloc(dev, sizeof(*probe_ent), GFP_KERNEL);
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if (probe_ent == NULL)
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return -ENOMEM;
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probe_ent->dev = pci_dev_to_dev(pdev);
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INIT_LIST_HEAD(&probe_ent->node);
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probe_ent->sht = &k2_sata_sht;
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probe_ent->port_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
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ATA_FLAG_MMIO | board_info->port_flags;
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probe_ent->port_ops = &k2_sata_ops;
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probe_ent->n_ports = 4;
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probe_ent->irq = pdev->irq;
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probe_ent->irq_flags = IRQF_SHARED;
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probe_ent->iomap = pcim_iomap_table(pdev);
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/* We don't care much about the PIO/UDMA masks, but the core won't like us
|
|
* if we don't fill these
|
|
*/
|
|
probe_ent->pio_mask = 0x1f;
|
|
probe_ent->mwdma_mask = 0x7;
|
|
probe_ent->udma_mask = 0x7f;
|
|
|
|
mmio_base = probe_ent->iomap[5];
|
|
|
|
/* different controllers have different number of ports - currently 4 or 8 */
|
|
/* All ports are on the same function. Multi-function device is no
|
|
* longer available. This should not be seen in any system. */
|
|
for (i = 0; i < board_info->n_ports; i++)
|
|
k2_sata_setup_port(&probe_ent->port[i],
|
|
mmio_base + i * K2_SATA_PORT_OFFSET);
|
|
|
|
/* Clear a magic bit in SCR1 according to Darwin, those help
|
|
* some funky seagate drives (though so far, those were already
|
|
* set by the firmware on the machines I had access to)
|
|
*/
|
|
writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
|
|
mmio_base + K2_SATA_SICR1_OFFSET);
|
|
|
|
/* Clear SATA error & interrupts we don't use */
|
|
writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
|
|
writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
|
|
|
|
pci_set_master(pdev);
|
|
|
|
if (!ata_device_add(probe_ent))
|
|
return -ENODEV;
|
|
|
|
devm_kfree(dev, probe_ent);
|
|
return 0;
|
|
}
|
|
|
|
/* 0x240 is device ID for Apple K2 device
|
|
* 0x241 is device ID for Serverworks Frodo4
|
|
* 0x242 is device ID for Serverworks Frodo8
|
|
* 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
|
|
* controller
|
|
* */
|
|
static const struct pci_device_id k2_sata_pci_tbl[] = {
|
|
{ PCI_VDEVICE(SERVERWORKS, 0x0240), board_svw4 },
|
|
{ PCI_VDEVICE(SERVERWORKS, 0x0241), board_svw4 },
|
|
{ PCI_VDEVICE(SERVERWORKS, 0x0242), board_svw8 },
|
|
{ PCI_VDEVICE(SERVERWORKS, 0x024a), board_svw4 },
|
|
{ PCI_VDEVICE(SERVERWORKS, 0x024b), board_svw4 },
|
|
|
|
{ }
|
|
};
|
|
|
|
static struct pci_driver k2_sata_pci_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = k2_sata_pci_tbl,
|
|
.probe = k2_sata_init_one,
|
|
.remove = ata_pci_remove_one,
|
|
};
|
|
|
|
static int __init k2_sata_init(void)
|
|
{
|
|
return pci_register_driver(&k2_sata_pci_driver);
|
|
}
|
|
|
|
static void __exit k2_sata_exit(void)
|
|
{
|
|
pci_unregister_driver(&k2_sata_pci_driver);
|
|
}
|
|
|
|
MODULE_AUTHOR("Benjamin Herrenschmidt");
|
|
MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
|
|
MODULE_VERSION(DRV_VERSION);
|
|
|
|
module_init(k2_sata_init);
|
|
module_exit(k2_sata_exit);
|