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6f52b16c5b
Many user space API headers are missing licensing information, which makes it hard for compliance tools to determine the correct license. By default are files without license information under the default license of the kernel, which is GPLV2. Marking them GPLV2 would exclude them from being included in non GPLV2 code, which is obviously not intended. The user space API headers fall under the syscall exception which is in the kernels COPYING file: NOTE! This copyright does *not* cover user programs that use kernel services by normal system calls - this is merely considered normal use of the kernel, and does *not* fall under the heading of "derived work". otherwise syscall usage would not be possible. Update the files which contain no license information with an SPDX license identifier. The chosen identifier is 'GPL-2.0 WITH Linux-syscall-note' which is the officially assigned identifier for the Linux syscall exception. SPDX license identifiers are a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. See the previous patch in this series for the methodology of how this patch was researched. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
620 lines
18 KiB
C
620 lines
18 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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*
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* Copyright (C) 2002,2003 Jun Nakajima <jun.nakajima@intel.com>
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* Copyright (C) 2002,2003 Suresh Siddha <suresh.b.siddha@intel.com>
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*/
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#ifndef _UAPI_ASM_IA64_GCC_INTRIN_H
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#define _UAPI_ASM_IA64_GCC_INTRIN_H
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#include <linux/types.h>
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#include <linux/compiler.h>
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/* define this macro to get some asm stmts included in 'c' files */
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#define ASM_SUPPORTED
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/* Optimization barrier */
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/* The "volatile" is due to gcc bugs */
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#define ia64_barrier() asm volatile ("":::"memory")
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#define ia64_stop() asm volatile (";;"::)
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#define ia64_invala_gr(regnum) asm volatile ("invala.e r%0" :: "i"(regnum))
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#define ia64_invala_fr(regnum) asm volatile ("invala.e f%0" :: "i"(regnum))
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#define ia64_flushrs() asm volatile ("flushrs;;":::"memory")
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#define ia64_loadrs() asm volatile ("loadrs;;":::"memory")
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extern void ia64_bad_param_for_setreg (void);
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extern void ia64_bad_param_for_getreg (void);
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#define ia64_native_setreg(regnum, val) \
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({ \
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switch (regnum) { \
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case _IA64_REG_PSR_L: \
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asm volatile ("mov psr.l=%0" :: "r"(val) : "memory"); \
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break; \
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case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC: \
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asm volatile ("mov ar%0=%1" :: \
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"i" (regnum - _IA64_REG_AR_KR0), \
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"r"(val): "memory"); \
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break; \
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case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1: \
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asm volatile ("mov cr%0=%1" :: \
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"i" (regnum - _IA64_REG_CR_DCR), \
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"r"(val): "memory" ); \
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break; \
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case _IA64_REG_SP: \
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asm volatile ("mov r12=%0" :: \
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"r"(val): "memory"); \
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break; \
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case _IA64_REG_GP: \
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asm volatile ("mov gp=%0" :: "r"(val) : "memory"); \
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break; \
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default: \
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ia64_bad_param_for_setreg(); \
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break; \
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} \
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})
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#define ia64_native_getreg(regnum) \
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({ \
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__u64 ia64_intri_res; \
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\
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switch (regnum) { \
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case _IA64_REG_GP: \
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asm volatile ("mov %0=gp" : "=r"(ia64_intri_res)); \
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break; \
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case _IA64_REG_IP: \
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asm volatile ("mov %0=ip" : "=r"(ia64_intri_res)); \
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break; \
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case _IA64_REG_PSR: \
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asm volatile ("mov %0=psr" : "=r"(ia64_intri_res)); \
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break; \
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case _IA64_REG_TP: /* for current() */ \
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ia64_intri_res = ia64_r13; \
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break; \
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case _IA64_REG_AR_KR0 ... _IA64_REG_AR_EC: \
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asm volatile ("mov %0=ar%1" : "=r" (ia64_intri_res) \
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: "i"(regnum - _IA64_REG_AR_KR0)); \
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break; \
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case _IA64_REG_CR_DCR ... _IA64_REG_CR_LRR1: \
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asm volatile ("mov %0=cr%1" : "=r" (ia64_intri_res) \
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: "i" (regnum - _IA64_REG_CR_DCR)); \
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break; \
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case _IA64_REG_SP: \
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asm volatile ("mov %0=sp" : "=r" (ia64_intri_res)); \
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break; \
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default: \
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ia64_bad_param_for_getreg(); \
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break; \
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} \
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ia64_intri_res; \
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})
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#define ia64_hint_pause 0
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#define ia64_hint(mode) \
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({ \
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switch (mode) { \
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case ia64_hint_pause: \
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asm volatile ("hint @pause" ::: "memory"); \
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break; \
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} \
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})
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/* Integer values for mux1 instruction */
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#define ia64_mux1_brcst 0
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#define ia64_mux1_mix 8
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#define ia64_mux1_shuf 9
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#define ia64_mux1_alt 10
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#define ia64_mux1_rev 11
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#define ia64_mux1(x, mode) \
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({ \
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__u64 ia64_intri_res; \
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\
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switch (mode) { \
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case ia64_mux1_brcst: \
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asm ("mux1 %0=%1,@brcst" : "=r" (ia64_intri_res) : "r" (x)); \
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break; \
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case ia64_mux1_mix: \
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asm ("mux1 %0=%1,@mix" : "=r" (ia64_intri_res) : "r" (x)); \
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break; \
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case ia64_mux1_shuf: \
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asm ("mux1 %0=%1,@shuf" : "=r" (ia64_intri_res) : "r" (x)); \
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break; \
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case ia64_mux1_alt: \
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asm ("mux1 %0=%1,@alt" : "=r" (ia64_intri_res) : "r" (x)); \
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break; \
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case ia64_mux1_rev: \
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asm ("mux1 %0=%1,@rev" : "=r" (ia64_intri_res) : "r" (x)); \
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break; \
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} \
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ia64_intri_res; \
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})
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#if __GNUC__ >= 4 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
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# define ia64_popcnt(x) __builtin_popcountl(x)
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#else
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# define ia64_popcnt(x) \
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({ \
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__u64 ia64_intri_res; \
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asm ("popcnt %0=%1" : "=r" (ia64_intri_res) : "r" (x)); \
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\
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ia64_intri_res; \
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})
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#endif
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#define ia64_getf_exp(x) \
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({ \
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long ia64_intri_res; \
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\
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asm ("getf.exp %0=%1" : "=r"(ia64_intri_res) : "f"(x)); \
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\
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ia64_intri_res; \
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})
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#define ia64_shrp(a, b, count) \
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({ \
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__u64 ia64_intri_res; \
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asm ("shrp %0=%1,%2,%3" : "=r"(ia64_intri_res) : "r"(a), "r"(b), "i"(count)); \
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ia64_intri_res; \
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})
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#define ia64_ldfs(regnum, x) \
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({ \
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register double __f__ asm ("f"#regnum); \
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asm volatile ("ldfs %0=[%1]" :"=f"(__f__): "r"(x)); \
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})
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#define ia64_ldfd(regnum, x) \
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({ \
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register double __f__ asm ("f"#regnum); \
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asm volatile ("ldfd %0=[%1]" :"=f"(__f__): "r"(x)); \
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})
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#define ia64_ldfe(regnum, x) \
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({ \
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register double __f__ asm ("f"#regnum); \
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asm volatile ("ldfe %0=[%1]" :"=f"(__f__): "r"(x)); \
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})
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#define ia64_ldf8(regnum, x) \
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({ \
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register double __f__ asm ("f"#regnum); \
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asm volatile ("ldf8 %0=[%1]" :"=f"(__f__): "r"(x)); \
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})
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#define ia64_ldf_fill(regnum, x) \
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({ \
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register double __f__ asm ("f"#regnum); \
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asm volatile ("ldf.fill %0=[%1]" :"=f"(__f__): "r"(x)); \
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})
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#define ia64_st4_rel_nta(m, val) \
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({ \
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asm volatile ("st4.rel.nta [%0] = %1\n\t" :: "r"(m), "r"(val)); \
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})
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#define ia64_stfs(x, regnum) \
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({ \
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register double __f__ asm ("f"#regnum); \
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asm volatile ("stfs [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
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})
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#define ia64_stfd(x, regnum) \
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({ \
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register double __f__ asm ("f"#regnum); \
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asm volatile ("stfd [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
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})
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#define ia64_stfe(x, regnum) \
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({ \
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register double __f__ asm ("f"#regnum); \
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asm volatile ("stfe [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
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})
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#define ia64_stf8(x, regnum) \
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({ \
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register double __f__ asm ("f"#regnum); \
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asm volatile ("stf8 [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
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})
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#define ia64_stf_spill(x, regnum) \
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({ \
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register double __f__ asm ("f"#regnum); \
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asm volatile ("stf.spill [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
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})
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#define ia64_fetchadd4_acq(p, inc) \
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({ \
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\
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__u64 ia64_intri_res; \
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asm volatile ("fetchadd4.acq %0=[%1],%2" \
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: "=r"(ia64_intri_res) : "r"(p), "i" (inc) \
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: "memory"); \
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\
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ia64_intri_res; \
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})
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#define ia64_fetchadd4_rel(p, inc) \
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({ \
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__u64 ia64_intri_res; \
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asm volatile ("fetchadd4.rel %0=[%1],%2" \
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: "=r"(ia64_intri_res) : "r"(p), "i" (inc) \
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: "memory"); \
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\
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ia64_intri_res; \
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})
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#define ia64_fetchadd8_acq(p, inc) \
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({ \
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\
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__u64 ia64_intri_res; \
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asm volatile ("fetchadd8.acq %0=[%1],%2" \
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: "=r"(ia64_intri_res) : "r"(p), "i" (inc) \
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: "memory"); \
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\
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ia64_intri_res; \
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})
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#define ia64_fetchadd8_rel(p, inc) \
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({ \
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__u64 ia64_intri_res; \
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asm volatile ("fetchadd8.rel %0=[%1],%2" \
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: "=r"(ia64_intri_res) : "r"(p), "i" (inc) \
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: "memory"); \
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\
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ia64_intri_res; \
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})
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#define ia64_xchg1(ptr,x) \
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({ \
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__u64 ia64_intri_res; \
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asm volatile ("xchg1 %0=[%1],%2" \
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: "=r" (ia64_intri_res) : "r" (ptr), "r" (x) : "memory"); \
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ia64_intri_res; \
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})
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#define ia64_xchg2(ptr,x) \
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({ \
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__u64 ia64_intri_res; \
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asm volatile ("xchg2 %0=[%1],%2" : "=r" (ia64_intri_res) \
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: "r" (ptr), "r" (x) : "memory"); \
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ia64_intri_res; \
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})
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#define ia64_xchg4(ptr,x) \
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({ \
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__u64 ia64_intri_res; \
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asm volatile ("xchg4 %0=[%1],%2" : "=r" (ia64_intri_res) \
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: "r" (ptr), "r" (x) : "memory"); \
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ia64_intri_res; \
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})
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#define ia64_xchg8(ptr,x) \
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({ \
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__u64 ia64_intri_res; \
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asm volatile ("xchg8 %0=[%1],%2" : "=r" (ia64_intri_res) \
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: "r" (ptr), "r" (x) : "memory"); \
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ia64_intri_res; \
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})
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#define ia64_cmpxchg1_acq(ptr, new, old) \
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({ \
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__u64 ia64_intri_res; \
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asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
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asm volatile ("cmpxchg1.acq %0=[%1],%2,ar.ccv": \
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"=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
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ia64_intri_res; \
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})
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#define ia64_cmpxchg1_rel(ptr, new, old) \
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({ \
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__u64 ia64_intri_res; \
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asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
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asm volatile ("cmpxchg1.rel %0=[%1],%2,ar.ccv": \
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"=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
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ia64_intri_res; \
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})
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#define ia64_cmpxchg2_acq(ptr, new, old) \
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({ \
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__u64 ia64_intri_res; \
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asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
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asm volatile ("cmpxchg2.acq %0=[%1],%2,ar.ccv": \
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"=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
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ia64_intri_res; \
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})
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#define ia64_cmpxchg2_rel(ptr, new, old) \
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({ \
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__u64 ia64_intri_res; \
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asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
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\
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asm volatile ("cmpxchg2.rel %0=[%1],%2,ar.ccv": \
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"=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
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ia64_intri_res; \
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})
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#define ia64_cmpxchg4_acq(ptr, new, old) \
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({ \
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__u64 ia64_intri_res; \
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asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
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asm volatile ("cmpxchg4.acq %0=[%1],%2,ar.ccv": \
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"=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
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ia64_intri_res; \
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})
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#define ia64_cmpxchg4_rel(ptr, new, old) \
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({ \
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__u64 ia64_intri_res; \
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asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
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asm volatile ("cmpxchg4.rel %0=[%1],%2,ar.ccv": \
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"=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
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ia64_intri_res; \
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})
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#define ia64_cmpxchg8_acq(ptr, new, old) \
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({ \
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__u64 ia64_intri_res; \
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asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
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asm volatile ("cmpxchg8.acq %0=[%1],%2,ar.ccv": \
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"=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
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ia64_intri_res; \
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})
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#define ia64_cmpxchg8_rel(ptr, new, old) \
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({ \
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__u64 ia64_intri_res; \
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asm volatile ("mov ar.ccv=%0;;" :: "rO"(old)); \
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\
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asm volatile ("cmpxchg8.rel %0=[%1],%2,ar.ccv": \
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"=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
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ia64_intri_res; \
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})
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#define ia64_mf() asm volatile ("mf" ::: "memory")
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#define ia64_mfa() asm volatile ("mf.a" ::: "memory")
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#define ia64_invala() asm volatile ("invala" ::: "memory")
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#define ia64_native_thash(addr) \
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({ \
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unsigned long ia64_intri_res; \
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asm volatile ("thash %0=%1" : "=r"(ia64_intri_res) : "r" (addr)); \
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ia64_intri_res; \
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})
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#define ia64_srlz_i() asm volatile (";; srlz.i ;;" ::: "memory")
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#define ia64_srlz_d() asm volatile (";; srlz.d" ::: "memory");
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#ifdef HAVE_SERIALIZE_DIRECTIVE
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# define ia64_dv_serialize_data() asm volatile (".serialize.data");
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# define ia64_dv_serialize_instruction() asm volatile (".serialize.instruction");
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#else
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# define ia64_dv_serialize_data()
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# define ia64_dv_serialize_instruction()
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#endif
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#define ia64_nop(x) asm volatile ("nop %0"::"i"(x));
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#define ia64_itci(addr) asm volatile ("itc.i %0;;" :: "r"(addr) : "memory")
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#define ia64_itcd(addr) asm volatile ("itc.d %0;;" :: "r"(addr) : "memory")
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#define ia64_itri(trnum, addr) asm volatile ("itr.i itr[%0]=%1" \
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:: "r"(trnum), "r"(addr) : "memory")
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#define ia64_itrd(trnum, addr) asm volatile ("itr.d dtr[%0]=%1" \
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:: "r"(trnum), "r"(addr) : "memory")
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#define ia64_tpa(addr) \
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({ \
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unsigned long ia64_pa; \
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asm volatile ("tpa %0 = %1" : "=r"(ia64_pa) : "r"(addr) : "memory"); \
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ia64_pa; \
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})
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#define __ia64_set_dbr(index, val) \
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asm volatile ("mov dbr[%0]=%1" :: "r"(index), "r"(val) : "memory")
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#define ia64_set_ibr(index, val) \
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asm volatile ("mov ibr[%0]=%1" :: "r"(index), "r"(val) : "memory")
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#define ia64_set_pkr(index, val) \
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asm volatile ("mov pkr[%0]=%1" :: "r"(index), "r"(val) : "memory")
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#define ia64_set_pmc(index, val) \
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asm volatile ("mov pmc[%0]=%1" :: "r"(index), "r"(val) : "memory")
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#define ia64_set_pmd(index, val) \
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asm volatile ("mov pmd[%0]=%1" :: "r"(index), "r"(val) : "memory")
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#define ia64_native_set_rr(index, val) \
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asm volatile ("mov rr[%0]=%1" :: "r"(index), "r"(val) : "memory");
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#define ia64_native_get_cpuid(index) \
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({ \
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unsigned long ia64_intri_res; \
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asm volatile ("mov %0=cpuid[%r1]" : "=r"(ia64_intri_res) : "rO"(index)); \
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ia64_intri_res; \
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})
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#define __ia64_get_dbr(index) \
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({ \
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|
unsigned long ia64_intri_res; \
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asm volatile ("mov %0=dbr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
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ia64_intri_res; \
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})
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|
|
|
#define ia64_get_ibr(index) \
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|
({ \
|
|
unsigned long ia64_intri_res; \
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asm volatile ("mov %0=ibr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
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ia64_intri_res; \
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|
})
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|
|
#define ia64_get_pkr(index) \
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|
({ \
|
|
unsigned long ia64_intri_res; \
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|
asm volatile ("mov %0=pkr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
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ia64_intri_res; \
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|
})
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|
|
|
#define ia64_get_pmc(index) \
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|
({ \
|
|
unsigned long ia64_intri_res; \
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|
asm volatile ("mov %0=pmc[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
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ia64_intri_res; \
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|
})
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|
|
|
|
|
#define ia64_native_get_pmd(index) \
|
|
({ \
|
|
unsigned long ia64_intri_res; \
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|
asm volatile ("mov %0=pmd[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
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|
ia64_intri_res; \
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|
})
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|
|
|
#define ia64_native_get_rr(index) \
|
|
({ \
|
|
unsigned long ia64_intri_res; \
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|
asm volatile ("mov %0=rr[%1]" : "=r"(ia64_intri_res) : "r" (index)); \
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|
ia64_intri_res; \
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|
})
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|
|
|
#define ia64_native_fc(addr) asm volatile ("fc %0" :: "r"(addr) : "memory")
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|
|
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|
#define ia64_sync_i() asm volatile (";; sync.i" ::: "memory")
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|
|
|
#define ia64_native_ssm(mask) asm volatile ("ssm %0":: "i"((mask)) : "memory")
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|
#define ia64_native_rsm(mask) asm volatile ("rsm %0":: "i"((mask)) : "memory")
|
|
#define ia64_sum(mask) asm volatile ("sum %0":: "i"((mask)) : "memory")
|
|
#define ia64_rum(mask) asm volatile ("rum %0":: "i"((mask)) : "memory")
|
|
|
|
#define ia64_ptce(addr) asm volatile ("ptc.e %0" :: "r"(addr))
|
|
|
|
#define ia64_native_ptcga(addr, size) \
|
|
do { \
|
|
asm volatile ("ptc.ga %0,%1" :: "r"(addr), "r"(size) : "memory"); \
|
|
ia64_dv_serialize_data(); \
|
|
} while (0)
|
|
|
|
#define ia64_ptcl(addr, size) \
|
|
do { \
|
|
asm volatile ("ptc.l %0,%1" :: "r"(addr), "r"(size) : "memory"); \
|
|
ia64_dv_serialize_data(); \
|
|
} while (0)
|
|
|
|
#define ia64_ptri(addr, size) \
|
|
asm volatile ("ptr.i %0,%1" :: "r"(addr), "r"(size) : "memory")
|
|
|
|
#define ia64_ptrd(addr, size) \
|
|
asm volatile ("ptr.d %0,%1" :: "r"(addr), "r"(size) : "memory")
|
|
|
|
#define ia64_ttag(addr) \
|
|
({ \
|
|
__u64 ia64_intri_res; \
|
|
asm volatile ("ttag %0=%1" : "=r"(ia64_intri_res) : "r" (addr)); \
|
|
ia64_intri_res; \
|
|
})
|
|
|
|
|
|
/* Values for lfhint in ia64_lfetch and ia64_lfetch_fault */
|
|
|
|
#define ia64_lfhint_none 0
|
|
#define ia64_lfhint_nt1 1
|
|
#define ia64_lfhint_nt2 2
|
|
#define ia64_lfhint_nta 3
|
|
|
|
#define ia64_lfetch(lfhint, y) \
|
|
({ \
|
|
switch (lfhint) { \
|
|
case ia64_lfhint_none: \
|
|
asm volatile ("lfetch [%0]" : : "r"(y)); \
|
|
break; \
|
|
case ia64_lfhint_nt1: \
|
|
asm volatile ("lfetch.nt1 [%0]" : : "r"(y)); \
|
|
break; \
|
|
case ia64_lfhint_nt2: \
|
|
asm volatile ("lfetch.nt2 [%0]" : : "r"(y)); \
|
|
break; \
|
|
case ia64_lfhint_nta: \
|
|
asm volatile ("lfetch.nta [%0]" : : "r"(y)); \
|
|
break; \
|
|
} \
|
|
})
|
|
|
|
#define ia64_lfetch_excl(lfhint, y) \
|
|
({ \
|
|
switch (lfhint) { \
|
|
case ia64_lfhint_none: \
|
|
asm volatile ("lfetch.excl [%0]" :: "r"(y)); \
|
|
break; \
|
|
case ia64_lfhint_nt1: \
|
|
asm volatile ("lfetch.excl.nt1 [%0]" :: "r"(y)); \
|
|
break; \
|
|
case ia64_lfhint_nt2: \
|
|
asm volatile ("lfetch.excl.nt2 [%0]" :: "r"(y)); \
|
|
break; \
|
|
case ia64_lfhint_nta: \
|
|
asm volatile ("lfetch.excl.nta [%0]" :: "r"(y)); \
|
|
break; \
|
|
} \
|
|
})
|
|
|
|
#define ia64_lfetch_fault(lfhint, y) \
|
|
({ \
|
|
switch (lfhint) { \
|
|
case ia64_lfhint_none: \
|
|
asm volatile ("lfetch.fault [%0]" : : "r"(y)); \
|
|
break; \
|
|
case ia64_lfhint_nt1: \
|
|
asm volatile ("lfetch.fault.nt1 [%0]" : : "r"(y)); \
|
|
break; \
|
|
case ia64_lfhint_nt2: \
|
|
asm volatile ("lfetch.fault.nt2 [%0]" : : "r"(y)); \
|
|
break; \
|
|
case ia64_lfhint_nta: \
|
|
asm volatile ("lfetch.fault.nta [%0]" : : "r"(y)); \
|
|
break; \
|
|
} \
|
|
})
|
|
|
|
#define ia64_lfetch_fault_excl(lfhint, y) \
|
|
({ \
|
|
switch (lfhint) { \
|
|
case ia64_lfhint_none: \
|
|
asm volatile ("lfetch.fault.excl [%0]" :: "r"(y)); \
|
|
break; \
|
|
case ia64_lfhint_nt1: \
|
|
asm volatile ("lfetch.fault.excl.nt1 [%0]" :: "r"(y)); \
|
|
break; \
|
|
case ia64_lfhint_nt2: \
|
|
asm volatile ("lfetch.fault.excl.nt2 [%0]" :: "r"(y)); \
|
|
break; \
|
|
case ia64_lfhint_nta: \
|
|
asm volatile ("lfetch.fault.excl.nta [%0]" :: "r"(y)); \
|
|
break; \
|
|
} \
|
|
})
|
|
|
|
#define ia64_native_intrin_local_irq_restore(x) \
|
|
do { \
|
|
asm volatile (";; cmp.ne p6,p7=%0,r0;;" \
|
|
"(p6) ssm psr.i;" \
|
|
"(p7) rsm psr.i;;" \
|
|
"(p6) srlz.d" \
|
|
:: "r"((x)) : "p6", "p7", "memory"); \
|
|
} while (0)
|
|
|
|
#endif /* _UAPI_ASM_IA64_GCC_INTRIN_H */
|