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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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699b477a0d
Tegra210 has an extra bank of peripheral clock registers. Add it to the generic peripheral clock code. Cc: Peter De Schrijver <pdeschrijver@nvidia.com> Cc: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
329 lines
8.1 KiB
C
329 lines
8.1 KiB
C
/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/clk/tegra.h>
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#include <linux/reset-controller.h>
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#include <soc/tegra/fuse.h>
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#include "clk.h"
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#define CLK_OUT_ENB_L 0x010
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#define CLK_OUT_ENB_H 0x014
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#define CLK_OUT_ENB_U 0x018
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#define CLK_OUT_ENB_V 0x360
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#define CLK_OUT_ENB_W 0x364
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#define CLK_OUT_ENB_X 0x280
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#define CLK_OUT_ENB_Y 0x298
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#define CLK_OUT_ENB_SET_L 0x320
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#define CLK_OUT_ENB_CLR_L 0x324
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#define CLK_OUT_ENB_SET_H 0x328
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#define CLK_OUT_ENB_CLR_H 0x32c
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#define CLK_OUT_ENB_SET_U 0x330
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#define CLK_OUT_ENB_CLR_U 0x334
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#define CLK_OUT_ENB_SET_V 0x440
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#define CLK_OUT_ENB_CLR_V 0x444
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#define CLK_OUT_ENB_SET_W 0x448
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#define CLK_OUT_ENB_CLR_W 0x44c
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#define CLK_OUT_ENB_SET_X 0x284
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#define CLK_OUT_ENB_CLR_X 0x288
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#define CLK_OUT_ENB_SET_Y 0x29c
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#define CLK_OUT_ENB_CLR_Y 0x2a0
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#define RST_DEVICES_L 0x004
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#define RST_DEVICES_H 0x008
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#define RST_DEVICES_U 0x00C
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#define RST_DFLL_DVCO 0x2F4
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#define RST_DEVICES_V 0x358
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#define RST_DEVICES_W 0x35C
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#define RST_DEVICES_X 0x28C
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#define RST_DEVICES_Y 0x2a4
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#define RST_DEVICES_SET_L 0x300
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#define RST_DEVICES_CLR_L 0x304
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#define RST_DEVICES_SET_H 0x308
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#define RST_DEVICES_CLR_H 0x30c
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#define RST_DEVICES_SET_U 0x310
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#define RST_DEVICES_CLR_U 0x314
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#define RST_DEVICES_SET_V 0x430
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#define RST_DEVICES_CLR_V 0x434
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#define RST_DEVICES_SET_W 0x438
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#define RST_DEVICES_CLR_W 0x43c
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#define RST_DEVICES_SET_X 0x290
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#define RST_DEVICES_CLR_X 0x294
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#define RST_DEVICES_SET_Y 0x2a8
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#define RST_DEVICES_CLR_Y 0x2ac
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/* Global data of Tegra CPU CAR ops */
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static struct tegra_cpu_car_ops dummy_car_ops;
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struct tegra_cpu_car_ops *tegra_cpu_car_ops = &dummy_car_ops;
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int *periph_clk_enb_refcnt;
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static int periph_banks;
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static struct clk **clks;
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static int clk_num;
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static struct clk_onecell_data clk_data;
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static struct tegra_clk_periph_regs periph_regs[] = {
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[0] = {
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.enb_reg = CLK_OUT_ENB_L,
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.enb_set_reg = CLK_OUT_ENB_SET_L,
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.enb_clr_reg = CLK_OUT_ENB_CLR_L,
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.rst_reg = RST_DEVICES_L,
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.rst_set_reg = RST_DEVICES_SET_L,
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.rst_clr_reg = RST_DEVICES_CLR_L,
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},
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[1] = {
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.enb_reg = CLK_OUT_ENB_H,
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.enb_set_reg = CLK_OUT_ENB_SET_H,
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.enb_clr_reg = CLK_OUT_ENB_CLR_H,
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.rst_reg = RST_DEVICES_H,
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.rst_set_reg = RST_DEVICES_SET_H,
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.rst_clr_reg = RST_DEVICES_CLR_H,
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},
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[2] = {
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.enb_reg = CLK_OUT_ENB_U,
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.enb_set_reg = CLK_OUT_ENB_SET_U,
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.enb_clr_reg = CLK_OUT_ENB_CLR_U,
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.rst_reg = RST_DEVICES_U,
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.rst_set_reg = RST_DEVICES_SET_U,
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.rst_clr_reg = RST_DEVICES_CLR_U,
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},
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[3] = {
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.enb_reg = CLK_OUT_ENB_V,
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.enb_set_reg = CLK_OUT_ENB_SET_V,
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.enb_clr_reg = CLK_OUT_ENB_CLR_V,
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.rst_reg = RST_DEVICES_V,
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.rst_set_reg = RST_DEVICES_SET_V,
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.rst_clr_reg = RST_DEVICES_CLR_V,
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},
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[4] = {
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.enb_reg = CLK_OUT_ENB_W,
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.enb_set_reg = CLK_OUT_ENB_SET_W,
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.enb_clr_reg = CLK_OUT_ENB_CLR_W,
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.rst_reg = RST_DEVICES_W,
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.rst_set_reg = RST_DEVICES_SET_W,
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.rst_clr_reg = RST_DEVICES_CLR_W,
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},
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[5] = {
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.enb_reg = CLK_OUT_ENB_X,
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.enb_set_reg = CLK_OUT_ENB_SET_X,
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.enb_clr_reg = CLK_OUT_ENB_CLR_X,
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.rst_reg = RST_DEVICES_X,
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.rst_set_reg = RST_DEVICES_SET_X,
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.rst_clr_reg = RST_DEVICES_CLR_X,
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},
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[6] = {
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.enb_reg = CLK_OUT_ENB_Y,
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.enb_set_reg = CLK_OUT_ENB_SET_Y,
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.enb_clr_reg = CLK_OUT_ENB_CLR_Y,
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.rst_reg = RST_DEVICES_Y,
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.rst_set_reg = RST_DEVICES_SET_Y,
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.rst_clr_reg = RST_DEVICES_CLR_Y,
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},
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};
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static void __iomem *clk_base;
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static int tegra_clk_rst_assert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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/*
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* If peripheral is on the APB bus then we must read the APB bus to
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* flush the write operation in apb bus. This will avoid peripheral
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* access after disabling clock. Since the reset driver has no
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* knowledge of which reset IDs represent which devices, simply do
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* this all the time.
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*/
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tegra_read_chipid();
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writel_relaxed(BIT(id % 32),
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clk_base + periph_regs[id / 32].rst_set_reg);
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return 0;
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}
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static int tegra_clk_rst_deassert(struct reset_controller_dev *rcdev,
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unsigned long id)
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{
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writel_relaxed(BIT(id % 32),
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clk_base + periph_regs[id / 32].rst_clr_reg);
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return 0;
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}
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struct tegra_clk_periph_regs *get_reg_bank(int clkid)
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{
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int reg_bank = clkid / 32;
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if (reg_bank < periph_banks)
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return &periph_regs[reg_bank];
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else {
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WARN_ON(1);
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return NULL;
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}
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}
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struct clk ** __init tegra_clk_init(void __iomem *regs, int num, int banks)
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{
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clk_base = regs;
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if (WARN_ON(banks > ARRAY_SIZE(periph_regs)))
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return NULL;
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periph_clk_enb_refcnt = kzalloc(32 * banks *
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sizeof(*periph_clk_enb_refcnt), GFP_KERNEL);
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if (!periph_clk_enb_refcnt)
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return NULL;
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periph_banks = banks;
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clks = kzalloc(num * sizeof(struct clk *), GFP_KERNEL);
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if (!clks)
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kfree(periph_clk_enb_refcnt);
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clk_num = num;
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return clks;
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}
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void __init tegra_init_dup_clks(struct tegra_clk_duplicate *dup_list,
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struct clk *clks[], int clk_max)
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{
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struct clk *clk;
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for (; dup_list->clk_id < clk_max; dup_list++) {
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clk = clks[dup_list->clk_id];
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dup_list->lookup.clk = clk;
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clkdev_add(&dup_list->lookup);
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}
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}
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void __init tegra_init_from_table(struct tegra_clk_init_table *tbl,
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struct clk *clks[], int clk_max)
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{
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struct clk *clk;
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for (; tbl->clk_id < clk_max; tbl++) {
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clk = clks[tbl->clk_id];
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if (IS_ERR_OR_NULL(clk)) {
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pr_err("%s: invalid entry %ld in clks array for id %d\n",
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__func__, PTR_ERR(clk), tbl->clk_id);
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WARN_ON(1);
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continue;
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}
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if (tbl->parent_id < clk_max) {
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struct clk *parent = clks[tbl->parent_id];
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if (clk_set_parent(clk, parent)) {
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pr_err("%s: Failed to set parent %s of %s\n",
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__func__, __clk_get_name(parent),
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__clk_get_name(clk));
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WARN_ON(1);
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}
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}
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if (tbl->rate)
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if (clk_set_rate(clk, tbl->rate)) {
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pr_err("%s: Failed to set rate %lu of %s\n",
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__func__, tbl->rate,
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__clk_get_name(clk));
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WARN_ON(1);
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}
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if (tbl->state)
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if (clk_prepare_enable(clk)) {
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pr_err("%s: Failed to enable %s\n", __func__,
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__clk_get_name(clk));
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WARN_ON(1);
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}
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}
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}
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static struct reset_control_ops rst_ops = {
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.assert = tegra_clk_rst_assert,
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.deassert = tegra_clk_rst_deassert,
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};
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static struct reset_controller_dev rst_ctlr = {
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.ops = &rst_ops,
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.owner = THIS_MODULE,
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.of_reset_n_cells = 1,
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};
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void __init tegra_add_of_provider(struct device_node *np)
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{
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int i;
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for (i = 0; i < clk_num; i++) {
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if (IS_ERR(clks[i])) {
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pr_err
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("Tegra clk %d: register failed with %ld\n",
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i, PTR_ERR(clks[i]));
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}
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if (!clks[i])
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clks[i] = ERR_PTR(-EINVAL);
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}
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clk_data.clks = clks;
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clk_data.clk_num = clk_num;
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of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
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rst_ctlr.of_node = np;
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rst_ctlr.nr_resets = periph_banks * 32;
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reset_controller_register(&rst_ctlr);
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}
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void __init tegra_register_devclks(struct tegra_devclk *dev_clks, int num)
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{
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int i;
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for (i = 0; i < num; i++, dev_clks++)
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clk_register_clkdev(clks[dev_clks->dt_id], dev_clks->con_id,
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dev_clks->dev_id);
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for (i = 0; i < clk_num; i++) {
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if (!IS_ERR_OR_NULL(clks[i]))
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clk_register_clkdev(clks[i], __clk_get_name(clks[i]),
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"tegra-clk-debug");
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}
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}
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struct clk ** __init tegra_lookup_dt_id(int clk_id,
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struct tegra_clk *tegra_clk)
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{
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if (tegra_clk[clk_id].present)
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return &clks[tegra_clk[clk_id].dt_id];
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else
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return NULL;
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}
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tegra_clk_apply_init_table_func tegra_clk_apply_init_table;
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static int __init tegra_clocks_apply_init_table(void)
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{
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if (!tegra_clk_apply_init_table)
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return 0;
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tegra_clk_apply_init_table();
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return 0;
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}
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arch_initcall(tegra_clocks_apply_init_table);
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