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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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63cc5a4da1
Currently the Tegra clock driver simplifies the clock tree somewhat by taking advantage of the fact that clk_m runs at the same frequency as the oscillator. While that's true on all currently supported SoCs, it does not apply to Tegra210 anymore. On Tegra210 clk_m is typically divided down from the oscillator frequency. To support that setup, add a separate clock for the oscillator that both clk_m and pll_ref derive from. Modify the tegra_osc_clk_init() function to take an additional divider parameter for clk_m. Existing SoCs always pass in 1, whereas Tegra210 will read the divider from a register in the clock & reset controller. Signed-off-by: Thierry Reding <treding@nvidia.com>
114 lines
2.8 KiB
C
114 lines
2.8 KiB
C
/*
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* Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/clk/tegra.h>
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#include "clk.h"
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#include "clk-id.h"
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#define OSC_CTRL 0x50
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#define OSC_CTRL_OSC_FREQ_SHIFT 28
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#define OSC_CTRL_PLL_REF_DIV_SHIFT 26
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int __init tegra_osc_clk_init(void __iomem *clk_base, struct tegra_clk *clks,
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unsigned long *input_freqs, unsigned int num,
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unsigned int clk_m_div, unsigned long *osc_freq,
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unsigned long *pll_ref_freq)
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{
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struct clk *clk, *osc;
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struct clk **dt_clk;
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u32 val, pll_ref_div;
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unsigned osc_idx;
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val = readl_relaxed(clk_base + OSC_CTRL);
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osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
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if (osc_idx < num)
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*osc_freq = input_freqs[osc_idx];
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else
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*osc_freq = 0;
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if (!*osc_freq) {
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WARN_ON(1);
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return -EINVAL;
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}
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osc = clk_register_fixed_rate(NULL, "osc", NULL, CLK_IS_ROOT,
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*osc_freq);
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dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m, clks);
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if (!dt_clk)
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return 0;
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clk = clk_register_fixed_factor(NULL, "clk_m", "osc",
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0, 1, clk_m_div);
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*dt_clk = clk;
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/* pll_ref */
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val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
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pll_ref_div = 1 << val;
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dt_clk = tegra_lookup_dt_id(tegra_clk_pll_ref, clks);
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if (!dt_clk)
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return 0;
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clk = clk_register_fixed_factor(NULL, "pll_ref", "osc",
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0, 1, pll_ref_div);
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*dt_clk = clk;
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if (pll_ref_freq)
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*pll_ref_freq = *osc_freq / pll_ref_div;
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return 0;
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}
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void __init tegra_fixed_clk_init(struct tegra_clk *tegra_clks)
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{
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struct clk *clk;
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struct clk **dt_clk;
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/* clk_32k */
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dt_clk = tegra_lookup_dt_id(tegra_clk_clk_32k, tegra_clks);
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if (dt_clk) {
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clk = clk_register_fixed_rate(NULL, "clk_32k", NULL,
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CLK_IS_ROOT, 32768);
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*dt_clk = clk;
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}
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/* clk_m_div2 */
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dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div2, tegra_clks);
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if (dt_clk) {
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clk = clk_register_fixed_factor(NULL, "clk_m_div2", "clk_m",
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CLK_SET_RATE_PARENT, 1, 2);
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*dt_clk = clk;
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}
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/* clk_m_div4 */
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dt_clk = tegra_lookup_dt_id(tegra_clk_clk_m_div4, tegra_clks);
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if (dt_clk) {
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clk = clk_register_fixed_factor(NULL, "clk_m_div4", "clk_m",
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CLK_SET_RATE_PARENT, 1, 4);
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*dt_clk = clk;
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}
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}
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