mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 21:55:36 +07:00
9ec1e66b80
There are currently 4 methods in intel_gvt_io_emulation_ops to emulate CFG/MMIO reading/writing for intel vGPU. A possibly better scope is: add 3 more methods for vgpu create/destroy/reset respectively, and rename the ops to 'intel_gvt_ops', then pass it to the MPT module (say the future kvmgt) to use: they are all methods for external usage. Signed-off-by: Jike Song <jike.song@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
305 lines
8.1 KiB
C
305 lines
8.1 KiB
C
/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Ke Yu
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* Kevin Tian <kevin.tian@intel.com>
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* Dexuan Cui
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*
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* Contributors:
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* Tina Zhang <tina.zhang@intel.com>
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* Min He <min.he@intel.com>
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* Niu Bing <bing.niu@intel.com>
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* Zhi Wang <zhi.a.wang@intel.com>
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*
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*/
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#include "i915_drv.h"
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#include "gvt.h"
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/**
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* intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset
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* @vgpu: a vGPU
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*
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* Returns:
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* Zero on success, negative error code if failed
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*/
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int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa)
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{
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u64 gttmmio_gpa = *(u64 *)(vgpu_cfg_space(vgpu) + PCI_BASE_ADDRESS_0) &
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~GENMASK(3, 0);
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return gpa - gttmmio_gpa;
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}
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#define reg_is_mmio(gvt, reg) \
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(reg >= 0 && reg < gvt->device_info.mmio_size)
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#define reg_is_gtt(gvt, reg) \
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(reg >= gvt->device_info.gtt_start_offset \
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&& reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt))
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/**
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* intel_vgpu_emulate_mmio_read - emulate MMIO read
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* @vgpu: a vGPU
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* @pa: guest physical address
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* @p_data: data return buffer
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* @bytes: access data length
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*
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* Returns:
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* Zero on success, negative error code if failed
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*/
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int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
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void *p_data, unsigned int bytes)
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{
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struct intel_gvt *gvt = vgpu->gvt;
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struct intel_gvt_mmio_info *mmio;
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unsigned int offset = 0;
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int ret = -EINVAL;
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mutex_lock(&gvt->lock);
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if (atomic_read(&vgpu->gtt.n_write_protected_guest_page)) {
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struct intel_vgpu_guest_page *gp;
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gp = intel_vgpu_find_guest_page(vgpu, pa >> PAGE_SHIFT);
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if (gp) {
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ret = intel_gvt_hypervisor_read_gpa(vgpu, pa,
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p_data, bytes);
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if (ret) {
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gvt_err("vgpu%d: guest page read error %d, "
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"gfn 0x%lx, pa 0x%llx, var 0x%x, len %d\n",
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vgpu->id, ret,
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gp->gfn, pa, *(u32 *)p_data, bytes);
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}
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mutex_unlock(&gvt->lock);
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return ret;
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}
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}
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offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
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if (WARN_ON(bytes > 8))
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goto err;
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if (reg_is_gtt(gvt, offset)) {
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if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
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goto err;
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if (WARN_ON(bytes != 4 && bytes != 8))
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goto err;
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if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
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goto err;
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ret = intel_vgpu_emulate_gtt_mmio_read(vgpu, offset,
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p_data, bytes);
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if (ret)
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goto err;
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mutex_unlock(&gvt->lock);
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return ret;
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}
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if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
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ret = intel_gvt_hypervisor_read_gpa(vgpu, pa, p_data, bytes);
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mutex_unlock(&gvt->lock);
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return ret;
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}
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if (WARN_ON(!reg_is_mmio(gvt, offset + bytes - 1)))
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goto err;
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mmio = intel_gvt_find_mmio_info(gvt, rounddown(offset, 4));
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if (!mmio && !vgpu->mmio.disable_warn_untrack) {
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gvt_err("vgpu%d: read untracked MMIO %x len %d val %x\n",
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vgpu->id, offset, bytes, *(u32 *)p_data);
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if (offset == 0x206c) {
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gvt_err("------------------------------------------\n");
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gvt_err("vgpu%d: likely triggers a gfx reset\n",
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vgpu->id);
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gvt_err("------------------------------------------\n");
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vgpu->mmio.disable_warn_untrack = true;
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}
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}
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if (!intel_gvt_mmio_is_unalign(gvt, offset)) {
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if (WARN_ON(!IS_ALIGNED(offset, bytes)))
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goto err;
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}
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if (mmio) {
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if (!intel_gvt_mmio_is_unalign(gvt, mmio->offset)) {
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if (WARN_ON(offset + bytes > mmio->offset + mmio->size))
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goto err;
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if (WARN_ON(mmio->offset != offset))
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goto err;
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}
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ret = mmio->read(vgpu, offset, p_data, bytes);
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} else
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ret = intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
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if (ret)
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goto err;
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intel_gvt_mmio_set_accessed(gvt, offset);
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mutex_unlock(&gvt->lock);
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return 0;
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err:
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gvt_err("vgpu%d: fail to emulate MMIO read %08x len %d\n",
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vgpu->id, offset, bytes);
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mutex_unlock(&gvt->lock);
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return ret;
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}
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/**
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* intel_vgpu_emulate_mmio_write - emulate MMIO write
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* @vgpu: a vGPU
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* @pa: guest physical address
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* @p_data: write data buffer
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* @bytes: access data length
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*
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* Returns:
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* Zero on success, negative error code if failed
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*/
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int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa,
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void *p_data, unsigned int bytes)
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{
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struct intel_gvt *gvt = vgpu->gvt;
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struct intel_gvt_mmio_info *mmio;
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unsigned int offset = 0;
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u32 old_vreg = 0, old_sreg = 0;
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int ret = -EINVAL;
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mutex_lock(&gvt->lock);
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if (atomic_read(&vgpu->gtt.n_write_protected_guest_page)) {
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struct intel_vgpu_guest_page *gp;
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gp = intel_vgpu_find_guest_page(vgpu, pa >> PAGE_SHIFT);
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if (gp) {
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ret = gp->handler(gp, pa, p_data, bytes);
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if (ret) {
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gvt_err("vgpu%d: guest page write error %d, "
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"gfn 0x%lx, pa 0x%llx, var 0x%x, len %d\n",
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vgpu->id, ret,
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gp->gfn, pa, *(u32 *)p_data, bytes);
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}
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mutex_unlock(&gvt->lock);
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return ret;
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}
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}
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offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
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if (WARN_ON(bytes > 8))
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goto err;
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if (reg_is_gtt(gvt, offset)) {
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if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
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goto err;
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if (WARN_ON(bytes != 4 && bytes != 8))
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goto err;
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if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
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goto err;
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ret = intel_vgpu_emulate_gtt_mmio_write(vgpu, offset,
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p_data, bytes);
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if (ret)
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goto err;
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mutex_unlock(&gvt->lock);
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return ret;
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}
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if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
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ret = intel_gvt_hypervisor_write_gpa(vgpu, pa, p_data, bytes);
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mutex_unlock(&gvt->lock);
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return ret;
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}
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mmio = intel_gvt_find_mmio_info(gvt, rounddown(offset, 4));
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if (!mmio && !vgpu->mmio.disable_warn_untrack)
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gvt_err("vgpu%d: write untracked MMIO %x len %d val %x\n",
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vgpu->id, offset, bytes, *(u32 *)p_data);
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if (!intel_gvt_mmio_is_unalign(gvt, offset)) {
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if (WARN_ON(!IS_ALIGNED(offset, bytes)))
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goto err;
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}
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if (mmio) {
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u64 ro_mask = mmio->ro_mask;
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if (!intel_gvt_mmio_is_unalign(gvt, mmio->offset)) {
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if (WARN_ON(offset + bytes > mmio->offset + mmio->size))
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goto err;
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if (WARN_ON(mmio->offset != offset))
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goto err;
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}
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if (intel_gvt_mmio_has_mode_mask(gvt, mmio->offset)) {
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old_vreg = vgpu_vreg(vgpu, offset);
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old_sreg = vgpu_sreg(vgpu, offset);
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}
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if (!ro_mask) {
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ret = mmio->write(vgpu, offset, p_data, bytes);
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} else {
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/* Protect RO bits like HW */
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u64 data = 0;
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/* all register bits are RO. */
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if (ro_mask == ~(u64)0) {
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gvt_err("vgpu%d: try to write RO reg %x\n",
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vgpu->id, offset);
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ret = 0;
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goto out;
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}
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/* keep the RO bits in the virtual register */
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memcpy(&data, p_data, bytes);
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data &= ~mmio->ro_mask;
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data |= vgpu_vreg(vgpu, offset) & mmio->ro_mask;
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ret = mmio->write(vgpu, offset, &data, bytes);
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}
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/* higher 16bits of mode ctl regs are mask bits for change */
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if (intel_gvt_mmio_has_mode_mask(gvt, mmio->offset)) {
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u32 mask = vgpu_vreg(vgpu, offset) >> 16;
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vgpu_vreg(vgpu, offset) = (old_vreg & ~mask)
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| (vgpu_vreg(vgpu, offset) & mask);
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vgpu_sreg(vgpu, offset) = (old_sreg & ~mask)
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| (vgpu_sreg(vgpu, offset) & mask);
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}
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} else
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ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data,
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bytes);
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if (ret)
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goto err;
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out:
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intel_gvt_mmio_set_accessed(gvt, offset);
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mutex_unlock(&gvt->lock);
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return 0;
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err:
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gvt_err("vgpu%d: fail to emulate MMIO write %08x len %d\n",
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vgpu->id, offset, bytes);
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mutex_unlock(&gvt->lock);
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return ret;
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}
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