Nicholas Piggin 30b49ec798 powerpc/64s/radix: Fix process table entry cache invalidation ... According to the architecture, the process table entry cache must be flushed with tlbie RIC=2. Currently the process table entry is set to invalid right before the PID is returned to the allocator, with no invalidation. This works on existing implementations that are known to not cache the process table entry for any except the current PIDR. It is architecturally correct and cleaner to invalidate with RIC=2 after clearing the process table entry and before the PID is returned to the allocator. This can be done in arch_exit_mmap that runs before the final flush, and to ensure the final flush (fullmm) is always a RIC=2 variant. Signed-off-by: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>		2017-11-06 16:48:10 +11:00
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asm	powerpc/64s/radix: Fix process table entry cache invalidation	2017-11-06 16:48:10 +11:00
uapi/asm	powerpc: Add PPC_FEATURE2_HTM_NO_SUSPEND	2017-10-20 11:10:58 +11:00