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dfc53c5e73
A previous commit resets the Context Status Buffer (CSB) read pointer in
ring init
commit c0a03a2e4c ("drm/i915: Reset CSB read pointer in ring init")
This is generally correct, but this pointer is not reset after
suspend/resume in some platforms (cht). In this case, the driver should
read the register value instead of resetting the sw read counter to 0.
Otherwise we process old events, leading to unwanted pre-emptions or
something worse.
But in other platforms (bdw) and also during GPU reset or power up, the
CSBWP is reset to 0x7 (an invalid number), and in this case the read
pointer should be set to 5 (the interrupt code will increment this
counter one more time, and will start reading from CSB[0]).
v2: When the CSB registers are reset, the read pointer needs to be set
to 5, otherwise the first write (CSB[0]) won't be read (Mika).
Replace magic numbers with GEN8_CSB_ENTRIES (6) and GEN8_CSB_PTR_MASK
(0x07).
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: stable@vger.kernel.org # v4.0+
Signed-off-by: Lei Shen <lei.shen@intel.com>
Signed-off-by: Deepak S <deepak.s@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
92 lines
3.6 KiB
C
92 lines
3.6 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _INTEL_LRC_H_
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#define _INTEL_LRC_H_
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#define GEN8_LR_CONTEXT_ALIGN 4096
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#define GEN8_CSB_ENTRIES 6
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#define GEN8_CSB_PTR_MASK 0x07
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/* Execlists regs */
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#define RING_ELSP(ring) ((ring)->mmio_base+0x230)
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#define RING_EXECLIST_STATUS(ring) ((ring)->mmio_base+0x234)
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#define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244)
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#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
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#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
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#define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
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#define RING_CONTEXT_STATUS_BUF(ring) ((ring)->mmio_base+0x370)
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#define RING_CONTEXT_STATUS_PTR(ring) ((ring)->mmio_base+0x3a0)
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/* Logical Rings */
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int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
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int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
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void intel_logical_ring_stop(struct intel_engine_cs *ring);
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void intel_logical_ring_cleanup(struct intel_engine_cs *ring);
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int intel_logical_rings_init(struct drm_device *dev);
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int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords);
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int logical_ring_flush_all_caches(struct drm_i915_gem_request *req);
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/**
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* intel_logical_ring_advance() - advance the ringbuffer tail
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* @ringbuf: Ringbuffer to advance.
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*
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* The tail is only updated in our logical ringbuffer struct.
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*/
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static inline void intel_logical_ring_advance(struct intel_ringbuffer *ringbuf)
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{
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ringbuf->tail &= ringbuf->size - 1;
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}
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/**
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* intel_logical_ring_emit() - write a DWORD to the ringbuffer.
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* @ringbuf: Ringbuffer to write to.
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* @data: DWORD to write.
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*/
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static inline void intel_logical_ring_emit(struct intel_ringbuffer *ringbuf,
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u32 data)
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{
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iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
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ringbuf->tail += 4;
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}
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/* Logical Ring Contexts */
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void intel_lr_context_free(struct intel_context *ctx);
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int intel_lr_context_deferred_create(struct intel_context *ctx,
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struct intel_engine_cs *ring);
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void intel_lr_context_unpin(struct drm_i915_gem_request *req);
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void intel_lr_context_reset(struct drm_device *dev,
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struct intel_context *ctx);
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/* Execlists */
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int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
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struct i915_execbuffer_params;
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int intel_execlists_submission(struct i915_execbuffer_params *params,
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struct drm_i915_gem_execbuffer2 *args,
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struct list_head *vmas);
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u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj);
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void intel_lrc_irq_handler(struct intel_engine_cs *ring);
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void intel_execlists_retire_requests(struct intel_engine_cs *ring);
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#endif /* _INTEL_LRC_H_ */
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