Ralf Baechle 554b7f56b9 MIPS: BMIPS: Flush the readahead cache after DMA. ... BMIPS 3300/435x/438x CPUs have a readahead cache that is separate from the L1/L2. During a DMA operation, accesses adjacent to a DMA buffer may cause parts of the DMA buffer to be prefetched into the RAC. To avoid possible coherency problems, flush the RAC upon DMA completion. Derived from Kevin Cernekee's https://patchwork.linux-mips.org/patch/9602/. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2015-04-01 17:22:04 +02:00
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dma-coherence.h	MIPS: BMIPS: Flush the readahead cache after DMA.	2015-04-01 17:22:04 +02:00
spaces.h	MIPS: BMIPS: Use a non-default FIXADDR_TOP setting	2015-04-01 17:21:41 +02:00