mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 09:30:53 +07:00
43250ddd75
Supporting AR8131, and AR8132. Signed-off-by: Jie Yang <jie.yang@atheros.com> Signed-off-by: David S. Miller <davem@davemloft.net>
528 lines
14 KiB
C
528 lines
14 KiB
C
/*
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* Copyright(c) 2007 Atheros Corporation. All rights reserved.
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*
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* Derived from Intel e1000 driver
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* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/mii.h>
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#include <linux/crc32.h>
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#include "atl1c.h"
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/*
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* check_eeprom_exist
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* return 1 if eeprom exist
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*/
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int atl1c_check_eeprom_exist(struct atl1c_hw *hw)
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{
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u32 data;
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AT_READ_REG(hw, REG_TWSI_DEBUG, &data);
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if (data & TWSI_DEBUG_DEV_EXIST)
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return 1;
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return 0;
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}
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void atl1c_hw_set_mac_addr(struct atl1c_hw *hw)
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{
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u32 value;
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/*
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* 00-0B-6A-F6-00-DC
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* 0: 6AF600DC 1: 000B
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* low dword
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*/
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value = (((u32)hw->mac_addr[2]) << 24) |
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(((u32)hw->mac_addr[3]) << 16) |
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(((u32)hw->mac_addr[4]) << 8) |
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(((u32)hw->mac_addr[5])) ;
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AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
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/* hight dword */
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value = (((u32)hw->mac_addr[0]) << 8) |
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(((u32)hw->mac_addr[1])) ;
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AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
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}
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/*
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* atl1c_get_permanent_address
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* return 0 if get valid mac address,
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*/
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static int atl1c_get_permanent_address(struct atl1c_hw *hw)
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{
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u32 addr[2];
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u32 i;
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u32 otp_ctrl_data;
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u32 twsi_ctrl_data;
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u8 eth_addr[ETH_ALEN];
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/* init */
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addr[0] = addr[1] = 0;
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AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data);
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if (atl1c_check_eeprom_exist(hw)) {
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/* Enable OTP CLK */
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if (!(otp_ctrl_data & OTP_CTRL_CLK_EN)) {
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otp_ctrl_data |= OTP_CTRL_CLK_EN;
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AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
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AT_WRITE_FLUSH(hw);
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msleep(1);
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}
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AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data);
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twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART;
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AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data);
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for (i = 0; i < AT_TWSI_EEPROM_TIMEOUT; i++) {
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msleep(10);
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AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data);
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if ((twsi_ctrl_data & TWSI_CTRL_SW_LDSTART) == 0)
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break;
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}
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if (i >= AT_TWSI_EEPROM_TIMEOUT)
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return -1;
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}
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/* Disable OTP_CLK */
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if (otp_ctrl_data & OTP_CTRL_CLK_EN) {
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otp_ctrl_data &= ~OTP_CTRL_CLK_EN;
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AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
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AT_WRITE_FLUSH(hw);
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msleep(1);
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}
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/* maybe MAC-address is from BIOS */
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AT_READ_REG(hw, REG_MAC_STA_ADDR, &addr[0]);
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AT_READ_REG(hw, REG_MAC_STA_ADDR + 4, &addr[1]);
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*(u32 *) ð_addr[2] = swab32(addr[0]);
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*(u16 *) ð_addr[0] = swab16(*(u16 *)&addr[1]);
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if (is_valid_ether_addr(eth_addr)) {
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memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
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return 0;
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}
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return -1;
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}
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bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value)
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{
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int i;
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int ret = false;
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u32 otp_ctrl_data;
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u32 control;
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u32 data;
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if (offset & 3)
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return ret; /* address do not align */
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AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data);
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if (!(otp_ctrl_data & OTP_CTRL_CLK_EN))
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AT_WRITE_REG(hw, REG_OTP_CTRL,
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(otp_ctrl_data | OTP_CTRL_CLK_EN));
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AT_WRITE_REG(hw, REG_EEPROM_DATA_LO, 0);
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control = (offset & EEPROM_CTRL_ADDR_MASK) << EEPROM_CTRL_ADDR_SHIFT;
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AT_WRITE_REG(hw, REG_EEPROM_CTRL, control);
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for (i = 0; i < 10; i++) {
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udelay(100);
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AT_READ_REG(hw, REG_EEPROM_CTRL, &control);
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if (control & EEPROM_CTRL_RW)
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break;
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}
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if (control & EEPROM_CTRL_RW) {
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AT_READ_REG(hw, REG_EEPROM_CTRL, &data);
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AT_READ_REG(hw, REG_EEPROM_DATA_LO, p_value);
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data = data & 0xFFFF;
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*p_value = swab32((data << 16) | (*p_value >> 16));
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ret = true;
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}
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if (!(otp_ctrl_data & OTP_CTRL_CLK_EN))
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AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data);
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return ret;
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}
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/*
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* Reads the adapter's MAC address from the EEPROM
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*
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* hw - Struct containing variables accessed by shared code
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*/
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int atl1c_read_mac_addr(struct atl1c_hw *hw)
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{
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int err = 0;
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err = atl1c_get_permanent_address(hw);
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if (err)
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random_ether_addr(hw->perm_mac_addr);
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memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr));
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return 0;
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}
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/*
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* atl1c_hash_mc_addr
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* purpose
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* set hash value for a multicast address
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* hash calcu processing :
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* 1. calcu 32bit CRC for multicast address
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* 2. reverse crc with MSB to LSB
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*/
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u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr)
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{
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u32 crc32;
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u32 value = 0;
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int i;
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crc32 = ether_crc_le(6, mc_addr);
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for (i = 0; i < 32; i++)
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value |= (((crc32 >> i) & 1) << (31 - i));
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return value;
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}
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/*
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* Sets the bit in the multicast table corresponding to the hash value.
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* hw - Struct containing variables accessed by shared code
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* hash_value - Multicast address hash value
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*/
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void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value)
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{
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u32 hash_bit, hash_reg;
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u32 mta;
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/*
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* The HASH Table is a register array of 2 32-bit registers.
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* It is treated like an array of 64 bits. We want to set
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* bit BitArray[hash_value]. So we figure out what register
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* the bit is in, read it, OR in the new bit, then write
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* back the new value. The register is determined by the
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* upper bit of the hash value and the bit within that
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* register are determined by the lower 5 bits of the value.
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*/
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hash_reg = (hash_value >> 31) & 0x1;
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hash_bit = (hash_value >> 26) & 0x1F;
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mta = AT_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg);
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mta |= (1 << hash_bit);
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AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta);
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}
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/*
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* Reads the value from a PHY register
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* hw - Struct containing variables accessed by shared code
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* reg_addr - address of the PHY register to read
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*/
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int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data)
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{
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u32 val;
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int i;
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val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
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MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW |
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MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
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AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
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for (i = 0; i < MDIO_WAIT_TIMES; i++) {
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udelay(2);
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AT_READ_REG(hw, REG_MDIO_CTRL, &val);
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if (!(val & (MDIO_START | MDIO_BUSY)))
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break;
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}
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if (!(val & (MDIO_START | MDIO_BUSY))) {
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*phy_data = (u16)val;
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return 0;
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}
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return -1;
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}
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/*
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* Writes a value to a PHY register
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* hw - Struct containing variables accessed by shared code
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* reg_addr - address of the PHY register to write
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* data - data to write to the PHY
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*/
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int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data)
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{
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int i;
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u32 val;
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val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
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(reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
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MDIO_SUP_PREAMBLE | MDIO_START |
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MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
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AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
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for (i = 0; i < MDIO_WAIT_TIMES; i++) {
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udelay(2);
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AT_READ_REG(hw, REG_MDIO_CTRL, &val);
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if (!(val & (MDIO_START | MDIO_BUSY)))
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break;
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}
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if (!(val & (MDIO_START | MDIO_BUSY)))
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return 0;
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return -1;
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}
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/*
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* Configures PHY autoneg and flow control advertisement settings
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*
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* hw - Struct containing variables accessed by shared code
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*/
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static int atl1c_phy_setup_adv(struct atl1c_hw *hw)
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{
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u16 mii_adv_data = ADVERTISE_DEFAULT_CAP & ~ADVERTISE_SPEED_MASK;
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u16 mii_giga_ctrl_data = GIGA_CR_1000T_DEFAULT_CAP &
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~GIGA_CR_1000T_SPEED_MASK;
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if (hw->autoneg_advertised & ADVERTISED_10baseT_Half)
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mii_adv_data |= ADVERTISE_10HALF;
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if (hw->autoneg_advertised & ADVERTISED_10baseT_Full)
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mii_adv_data |= ADVERTISE_10FULL;
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if (hw->autoneg_advertised & ADVERTISED_100baseT_Half)
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mii_adv_data |= ADVERTISE_100HALF;
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if (hw->autoneg_advertised & ADVERTISED_100baseT_Full)
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mii_adv_data |= ADVERTISE_100FULL;
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if (hw->autoneg_advertised & ADVERTISED_Autoneg)
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mii_adv_data |= ADVERTISE_10HALF | ADVERTISE_10FULL |
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ADVERTISE_100HALF | ADVERTISE_100FULL;
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if (hw->ctrl_flags & ATL1C_LINK_CAP_1000M) {
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if (hw->autoneg_advertised & ADVERTISED_1000baseT_Half)
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mii_giga_ctrl_data |= ADVERTISE_1000HALF;
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if (hw->autoneg_advertised & ADVERTISED_1000baseT_Full)
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mii_giga_ctrl_data |= ADVERTISE_1000FULL;
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if (hw->autoneg_advertised & ADVERTISED_Autoneg)
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mii_giga_ctrl_data |= ADVERTISE_1000HALF |
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ADVERTISE_1000FULL;
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}
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if (atl1c_write_phy_reg(hw, MII_ADVERTISE, mii_adv_data) != 0 ||
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atl1c_write_phy_reg(hw, MII_GIGA_CR, mii_giga_ctrl_data) != 0)
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return -1;
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return 0;
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}
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void atl1c_phy_disable(struct atl1c_hw *hw)
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{
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AT_WRITE_REGW(hw, REG_GPHY_CTRL,
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GPHY_CTRL_PW_WOL_DIS | GPHY_CTRL_EXT_RESET);
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}
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static void atl1c_phy_magic_data(struct atl1c_hw *hw)
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{
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u16 data;
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data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE |
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((1 & ANA_INTERVAL_SEL_TIMER_MASK) <<
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ANA_INTERVAL_SEL_TIMER_SHIFT);
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atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_18);
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atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
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data = (2 & ANA_SERDES_CDR_BW_MASK) | ANA_MS_PAD_DBG |
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ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL |
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ANA_SERDES_EN_LCKDT;
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atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_5);
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atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
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data = (44 & ANA_LONG_CABLE_TH_100_MASK) |
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((33 & ANA_SHORT_CABLE_TH_100_MASK) <<
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ANA_SHORT_CABLE_TH_100_SHIFT) | ANA_BP_BAD_LINK_ACCUM |
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ANA_BP_SMALL_BW;
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atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_54);
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atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
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data = (11 & ANA_IECHO_ADJ_MASK) | ((11 & ANA_IECHO_ADJ_MASK) <<
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ANA_IECHO_ADJ_2_SHIFT) | ((8 & ANA_IECHO_ADJ_MASK) <<
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ANA_IECHO_ADJ_1_SHIFT) | ((8 & ANA_IECHO_ADJ_MASK) <<
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ANA_IECHO_ADJ_0_SHIFT);
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atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_4);
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atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
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data = ANA_RESTART_CAL | ((7 & ANA_MANUL_SWICH_ON_MASK) <<
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ANA_MANUL_SWICH_ON_SHIFT) | ANA_MAN_ENABLE |
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ANA_SEL_HSP | ANA_EN_HB | ANA_OEN_125M;
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atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_0);
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atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
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if (hw->ctrl_flags & ATL1C_HIB_DISABLE) {
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atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_41);
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if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &data) != 0)
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return;
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data &= ~ANA_TOP_PS_EN;
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atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
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atl1c_write_phy_reg(hw, MII_DBG_ADDR, MII_ANA_CTRL_11);
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if (atl1c_read_phy_reg(hw, MII_DBG_DATA, &data) != 0)
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return;
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data &= ~ANA_PS_HIB_EN;
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atl1c_write_phy_reg(hw, MII_DBG_DATA, data);
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}
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}
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int atl1c_phy_reset(struct atl1c_hw *hw)
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{
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struct atl1c_adapter *adapter = hw->adapter;
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struct pci_dev *pdev = adapter->pdev;
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u32 phy_ctrl_data = GPHY_CTRL_DEFAULT;
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u32 mii_ier_data = IER_LINK_UP | IER_LINK_DOWN;
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int err;
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if (hw->ctrl_flags & ATL1C_HIB_DISABLE)
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phy_ctrl_data &= ~GPHY_CTRL_HIB_EN;
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AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
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AT_WRITE_FLUSH(hw);
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msleep(40);
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phy_ctrl_data |= GPHY_CTRL_EXT_RESET;
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AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data);
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AT_WRITE_FLUSH(hw);
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msleep(10);
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/*Enable PHY LinkChange Interrupt */
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err = atl1c_write_phy_reg(hw, MII_IER, mii_ier_data);
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if (err) {
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if (netif_msg_hw(adapter))
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dev_err(&pdev->dev,
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"Error enable PHY linkChange Interrupt\n");
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return err;
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}
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if (!(hw->ctrl_flags & ATL1C_FPGA_VERSION))
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atl1c_phy_magic_data(hw);
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return 0;
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}
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int atl1c_phy_init(struct atl1c_hw *hw)
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{
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struct atl1c_adapter *adapter = (struct atl1c_adapter *)hw->adapter;
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struct pci_dev *pdev = adapter->pdev;
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int ret_val;
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u16 mii_bmcr_data = BMCR_RESET;
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u16 phy_id1, phy_id2;
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if ((atl1c_read_phy_reg(hw, MII_PHYSID1, &phy_id1) != 0) ||
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(atl1c_read_phy_reg(hw, MII_PHYSID2, &phy_id2) != 0)) {
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if (netif_msg_link(adapter))
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dev_err(&pdev->dev, "Error get phy ID\n");
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return -1;
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}
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switch (hw->media_type) {
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case MEDIA_TYPE_AUTO_SENSOR:
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ret_val = atl1c_phy_setup_adv(hw);
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if (ret_val) {
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if (netif_msg_link(adapter))
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dev_err(&pdev->dev,
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"Error Setting up Auto-Negotiation\n");
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return ret_val;
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}
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mii_bmcr_data |= BMCR_AUTO_NEG_EN | BMCR_RESTART_AUTO_NEG;
|
|
break;
|
|
case MEDIA_TYPE_100M_FULL:
|
|
mii_bmcr_data |= BMCR_SPEED_100 | BMCR_FULL_DUPLEX;
|
|
break;
|
|
case MEDIA_TYPE_100M_HALF:
|
|
mii_bmcr_data |= BMCR_SPEED_100;
|
|
break;
|
|
case MEDIA_TYPE_10M_FULL:
|
|
mii_bmcr_data |= BMCR_SPEED_10 | BMCR_FULL_DUPLEX;
|
|
break;
|
|
case MEDIA_TYPE_10M_HALF:
|
|
mii_bmcr_data |= BMCR_SPEED_10;
|
|
break;
|
|
default:
|
|
if (netif_msg_link(adapter))
|
|
dev_err(&pdev->dev, "Wrong Media type %d\n",
|
|
hw->media_type);
|
|
return -1;
|
|
break;
|
|
}
|
|
|
|
ret_val = atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data);
|
|
if (ret_val)
|
|
return ret_val;
|
|
hw->phy_configured = true;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Detects the current speed and duplex settings of the hardware.
|
|
*
|
|
* hw - Struct containing variables accessed by shared code
|
|
* speed - Speed of the connection
|
|
* duplex - Duplex setting of the connection
|
|
*/
|
|
int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex)
|
|
{
|
|
int err;
|
|
u16 phy_data;
|
|
|
|
/* Read PHY Specific Status Register (17) */
|
|
err = atl1c_read_phy_reg(hw, MII_GIGA_PSSR, &phy_data);
|
|
if (err)
|
|
return err;
|
|
|
|
if (!(phy_data & GIGA_PSSR_SPD_DPLX_RESOLVED))
|
|
return -1;
|
|
|
|
switch (phy_data & GIGA_PSSR_SPEED) {
|
|
case GIGA_PSSR_1000MBS:
|
|
*speed = SPEED_1000;
|
|
break;
|
|
case GIGA_PSSR_100MBS:
|
|
*speed = SPEED_100;
|
|
break;
|
|
case GIGA_PSSR_10MBS:
|
|
*speed = SPEED_10;
|
|
break;
|
|
default:
|
|
return -1;
|
|
break;
|
|
}
|
|
|
|
if (phy_data & GIGA_PSSR_DPLX)
|
|
*duplex = FULL_DUPLEX;
|
|
else
|
|
*duplex = HALF_DUPLEX;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int atl1c_restart_autoneg(struct atl1c_hw *hw)
|
|
{
|
|
int err = 0;
|
|
u16 mii_bmcr_data = BMCR_RESET;
|
|
|
|
err = atl1c_phy_setup_adv(hw);
|
|
if (err)
|
|
return err;
|
|
mii_bmcr_data |= BMCR_AUTO_NEG_EN | BMCR_RESTART_AUTO_NEG;
|
|
|
|
return atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data);
|
|
}
|