mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 22:21:59 +07:00
71c8fc0c96
When rewriting swapper using nG mappings, we must performance cache
maintenance around each page table access in order to avoid coherency
problems with the host's cacheable alias under KVM. To ensure correct
ordering of the maintenance with respect to Device memory accesses made
with the Stage-1 MMU disabled, DMBs need to be added between the
maintenance and the corresponding memory access.
This patch adds a missing DMB between writing a new page table entry and
performing a clean+invalidate on the same line.
Fixes: f992b4dfd5 ("arm64: kpti: Add ->enable callback to remap swapper using nG mappings")
Cc: <stable@vger.kernel.org> # 4.16.x-
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
465 lines
10 KiB
ArmAsm
465 lines
10 KiB
ArmAsm
/*
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* Based on arch/arm/mm/proc.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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* Copyright (C) 2012 ARM Ltd.
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* Author: Catalin Marinas <catalin.marinas@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/cpufeature.h>
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#include <asm/alternative.h>
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#ifdef CONFIG_ARM64_64K_PAGES
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#define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K
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#elif defined(CONFIG_ARM64_16K_PAGES)
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#define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K
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#else /* CONFIG_ARM64_4K_PAGES */
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#define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K
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#endif
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#ifdef CONFIG_RANDOMIZE_BASE
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#define TCR_KASLR_FLAGS TCR_NFD1
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#else
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#define TCR_KASLR_FLAGS 0
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#endif
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#define TCR_SMP_FLAGS TCR_SHARED
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/* PTWs cacheable, inner/outer WBWA */
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#define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
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#define MAIR(attr, mt) ((attr) << ((mt) * 8))
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/*
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* cpu_do_idle()
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*
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* Idle the processor (wait for interrupt).
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*/
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ENTRY(cpu_do_idle)
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dsb sy // WFI may enter a low-power mode
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wfi
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ret
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ENDPROC(cpu_do_idle)
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#ifdef CONFIG_CPU_PM
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/**
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* cpu_do_suspend - save CPU registers context
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*
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* x0: virtual address of context pointer
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*/
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ENTRY(cpu_do_suspend)
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mrs x2, tpidr_el0
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mrs x3, tpidrro_el0
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mrs x4, contextidr_el1
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mrs x5, cpacr_el1
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mrs x6, tcr_el1
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mrs x7, vbar_el1
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mrs x8, mdscr_el1
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mrs x9, oslsr_el1
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mrs x10, sctlr_el1
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alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
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mrs x11, tpidr_el1
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alternative_else
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mrs x11, tpidr_el2
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alternative_endif
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mrs x12, sp_el0
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stp x2, x3, [x0]
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stp x4, xzr, [x0, #16]
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stp x5, x6, [x0, #32]
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stp x7, x8, [x0, #48]
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stp x9, x10, [x0, #64]
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stp x11, x12, [x0, #80]
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ret
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ENDPROC(cpu_do_suspend)
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/**
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* cpu_do_resume - restore CPU register context
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*
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* x0: Address of context pointer
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*/
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.pushsection ".idmap.text", "awx"
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ENTRY(cpu_do_resume)
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ldp x2, x3, [x0]
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ldp x4, x5, [x0, #16]
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ldp x6, x8, [x0, #32]
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ldp x9, x10, [x0, #48]
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ldp x11, x12, [x0, #64]
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ldp x13, x14, [x0, #80]
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msr tpidr_el0, x2
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msr tpidrro_el0, x3
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msr contextidr_el1, x4
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msr cpacr_el1, x6
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/* Don't change t0sz here, mask those bits when restoring */
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mrs x5, tcr_el1
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bfi x8, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
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msr tcr_el1, x8
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msr vbar_el1, x9
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/*
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* __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
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* debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
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* exception. Mask them until local_daif_restore() in cpu_suspend()
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* resets them.
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*/
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disable_daif
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msr mdscr_el1, x10
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msr sctlr_el1, x12
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alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
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msr tpidr_el1, x13
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alternative_else
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msr tpidr_el2, x13
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alternative_endif
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msr sp_el0, x14
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/*
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* Restore oslsr_el1 by writing oslar_el1
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*/
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ubfx x11, x11, #1, #1
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msr oslar_el1, x11
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reset_pmuserenr_el0 x0 // Disable PMU access from EL0
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alternative_if ARM64_HAS_RAS_EXTN
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msr_s SYS_DISR_EL1, xzr
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alternative_else_nop_endif
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isb
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ret
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ENDPROC(cpu_do_resume)
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.popsection
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#endif
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/*
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* cpu_do_switch_mm(pgd_phys, tsk)
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*
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* Set the translation table base pointer to be pgd_phys.
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*
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* - pgd_phys - physical address of new TTB
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*/
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ENTRY(cpu_do_switch_mm)
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mrs x2, ttbr1_el1
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mmid x1, x1 // get mm->context.id
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phys_to_ttbr x3, x0
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#ifdef CONFIG_ARM64_SW_TTBR0_PAN
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bfi x3, x1, #48, #16 // set the ASID field in TTBR0
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#endif
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bfi x2, x1, #48, #16 // set the ASID
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msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set)
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isb
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msr ttbr0_el1, x3 // now update TTBR0
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isb
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b post_ttbr_update_workaround // Back to C code...
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ENDPROC(cpu_do_switch_mm)
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.pushsection ".idmap.text", "awx"
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.macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
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adrp \tmp1, empty_zero_page
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phys_to_ttbr \tmp2, \tmp1
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msr ttbr1_el1, \tmp2
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isb
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tlbi vmalle1
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dsb nsh
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isb
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.endm
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/*
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* void idmap_cpu_replace_ttbr1(phys_addr_t new_pgd)
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*
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* This is the low-level counterpart to cpu_replace_ttbr1, and should not be
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* called by anything else. It can only be executed from a TTBR0 mapping.
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*/
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ENTRY(idmap_cpu_replace_ttbr1)
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save_and_disable_daif flags=x2
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__idmap_cpu_set_reserved_ttbr1 x1, x3
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phys_to_ttbr x3, x0
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msr ttbr1_el1, x3
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isb
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restore_daif x2
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ret
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ENDPROC(idmap_cpu_replace_ttbr1)
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.popsection
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#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
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.pushsection ".idmap.text", "awx"
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.macro __idmap_kpti_get_pgtable_ent, type
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dc cvac, cur_\()\type\()p // Ensure any existing dirty
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dmb sy // lines are written back before
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ldr \type, [cur_\()\type\()p] // loading the entry
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tbz \type, #0, skip_\()\type // Skip invalid and
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tbnz \type, #11, skip_\()\type // non-global entries
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.endm
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.macro __idmap_kpti_put_pgtable_ent_ng, type
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orr \type, \type, #PTE_NG // Same bit for blocks and pages
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str \type, [cur_\()\type\()p] // Update the entry and ensure
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dmb sy // that it is visible to all
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dc civac, cur_\()\type\()p // CPUs.
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.endm
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/*
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* void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
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*
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* Called exactly once from stop_machine context by each CPU found during boot.
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*/
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__idmap_kpti_flag:
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.long 1
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ENTRY(idmap_kpti_install_ng_mappings)
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cpu .req w0
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num_cpus .req w1
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swapper_pa .req x2
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swapper_ttb .req x3
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flag_ptr .req x4
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cur_pgdp .req x5
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end_pgdp .req x6
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pgd .req x7
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cur_pudp .req x8
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end_pudp .req x9
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pud .req x10
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cur_pmdp .req x11
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end_pmdp .req x12
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pmd .req x13
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cur_ptep .req x14
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end_ptep .req x15
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pte .req x16
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mrs swapper_ttb, ttbr1_el1
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adr flag_ptr, __idmap_kpti_flag
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cbnz cpu, __idmap_kpti_secondary
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/* We're the boot CPU. Wait for the others to catch up */
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sevl
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1: wfe
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ldaxr w18, [flag_ptr]
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eor w18, w18, num_cpus
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cbnz w18, 1b
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/* We need to walk swapper, so turn off the MMU. */
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pre_disable_mmu_workaround
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mrs x18, sctlr_el1
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bic x18, x18, #SCTLR_ELx_M
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msr sctlr_el1, x18
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isb
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/* Everybody is enjoying the idmap, so we can rewrite swapper. */
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/* PGD */
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mov cur_pgdp, swapper_pa
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add end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
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do_pgd: __idmap_kpti_get_pgtable_ent pgd
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tbnz pgd, #1, walk_puds
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next_pgd:
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__idmap_kpti_put_pgtable_ent_ng pgd
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skip_pgd:
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add cur_pgdp, cur_pgdp, #8
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cmp cur_pgdp, end_pgdp
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b.ne do_pgd
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/* Publish the updated tables and nuke all the TLBs */
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dsb sy
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tlbi vmalle1is
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dsb ish
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isb
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/* We're done: fire up the MMU again */
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mrs x18, sctlr_el1
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orr x18, x18, #SCTLR_ELx_M
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msr sctlr_el1, x18
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isb
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/* Set the flag to zero to indicate that we're all done */
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str wzr, [flag_ptr]
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ret
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/* PUD */
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walk_puds:
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.if CONFIG_PGTABLE_LEVELS > 3
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pte_to_phys cur_pudp, pgd
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add end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
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do_pud: __idmap_kpti_get_pgtable_ent pud
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tbnz pud, #1, walk_pmds
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next_pud:
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__idmap_kpti_put_pgtable_ent_ng pud
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skip_pud:
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add cur_pudp, cur_pudp, 8
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cmp cur_pudp, end_pudp
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b.ne do_pud
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b next_pgd
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.else /* CONFIG_PGTABLE_LEVELS <= 3 */
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mov pud, pgd
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b walk_pmds
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next_pud:
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b next_pgd
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.endif
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/* PMD */
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walk_pmds:
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.if CONFIG_PGTABLE_LEVELS > 2
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pte_to_phys cur_pmdp, pud
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add end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
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do_pmd: __idmap_kpti_get_pgtable_ent pmd
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tbnz pmd, #1, walk_ptes
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next_pmd:
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__idmap_kpti_put_pgtable_ent_ng pmd
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skip_pmd:
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add cur_pmdp, cur_pmdp, #8
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cmp cur_pmdp, end_pmdp
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b.ne do_pmd
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b next_pud
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.else /* CONFIG_PGTABLE_LEVELS <= 2 */
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mov pmd, pud
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b walk_ptes
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next_pmd:
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b next_pud
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.endif
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/* PTE */
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walk_ptes:
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pte_to_phys cur_ptep, pmd
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add end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
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do_pte: __idmap_kpti_get_pgtable_ent pte
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__idmap_kpti_put_pgtable_ent_ng pte
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skip_pte:
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add cur_ptep, cur_ptep, #8
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cmp cur_ptep, end_ptep
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b.ne do_pte
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b next_pmd
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/* Secondary CPUs end up here */
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__idmap_kpti_secondary:
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/* Uninstall swapper before surgery begins */
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__idmap_cpu_set_reserved_ttbr1 x18, x17
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/* Increment the flag to let the boot CPU we're ready */
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1: ldxr w18, [flag_ptr]
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add w18, w18, #1
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stxr w17, w18, [flag_ptr]
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cbnz w17, 1b
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/* Wait for the boot CPU to finish messing around with swapper */
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sevl
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1: wfe
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ldxr w18, [flag_ptr]
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cbnz w18, 1b
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/* All done, act like nothing happened */
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msr ttbr1_el1, swapper_ttb
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isb
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ret
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.unreq cpu
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.unreq num_cpus
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.unreq swapper_pa
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.unreq swapper_ttb
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.unreq flag_ptr
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.unreq cur_pgdp
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.unreq end_pgdp
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.unreq pgd
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.unreq cur_pudp
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.unreq end_pudp
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.unreq pud
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.unreq cur_pmdp
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.unreq end_pmdp
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.unreq pmd
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.unreq cur_ptep
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.unreq end_ptep
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.unreq pte
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ENDPROC(idmap_kpti_install_ng_mappings)
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.popsection
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#endif
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/*
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* __cpu_setup
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*
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* Initialise the processor for turning the MMU on. Return in x0 the
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* value of the SCTLR_EL1 register.
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*/
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.pushsection ".idmap.text", "awx"
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ENTRY(__cpu_setup)
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tlbi vmalle1 // Invalidate local TLB
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dsb nsh
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mov x0, #3 << 20
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msr cpacr_el1, x0 // Enable FP/ASIMD
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mov x0, #1 << 12 // Reset mdscr_el1 and disable
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msr mdscr_el1, x0 // access to the DCC from EL0
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isb // Unmask debug exceptions now,
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enable_dbg // since this is per-cpu
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reset_pmuserenr_el0 x0 // Disable PMU access from EL0
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/*
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* Memory region attributes for LPAE:
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*
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* n = AttrIndx[2:0]
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* n MAIR
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* DEVICE_nGnRnE 000 00000000
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* DEVICE_nGnRE 001 00000100
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* DEVICE_GRE 010 00001100
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* NORMAL_NC 011 01000100
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* NORMAL 100 11111111
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* NORMAL_WT 101 10111011
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*/
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ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
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MAIR(0x04, MT_DEVICE_nGnRE) | \
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MAIR(0x0c, MT_DEVICE_GRE) | \
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MAIR(0x44, MT_NORMAL_NC) | \
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MAIR(0xff, MT_NORMAL) | \
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MAIR(0xbb, MT_NORMAL_WT)
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msr mair_el1, x5
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/*
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* Prepare SCTLR
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*/
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mov_q x0, SCTLR_EL1_SET
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/*
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* Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
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* both user and kernel.
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*/
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ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
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TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
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TCR_TBI0 | TCR_A1
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tcr_set_idmap_t0sz x10, x9
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/*
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* Set the IPS bits in TCR_EL1.
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*/
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tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6
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#ifdef CONFIG_ARM64_HW_AFDBM
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/*
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* Enable hardware update of the Access Flags bit.
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* Hardware dirty bit management is enabled later,
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* via capabilities.
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*/
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mrs x9, ID_AA64MMFR1_EL1
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and x9, x9, #0xf
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cbz x9, 1f
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orr x10, x10, #TCR_HA // hardware Access flag update
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1:
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#endif /* CONFIG_ARM64_HW_AFDBM */
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msr tcr_el1, x10
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ret // return to head.S
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ENDPROC(__cpu_setup)
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