mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-20 10:59:04 +07:00
95d8b41c76
Add the control register as the base for the clock nodes which are missing them. This squashes the following warnings of the effect when built with W=1: arch/arm/boot/dts/keystone-k2e-evm.dtb: Warning (unit_address_vs_reg): Node /soc@0/clocks/clkusb1 has a reg or ranges property, but no unit name arch/arm/boot/dts/keystone-k2e-evm.dtb: Warning (unit_address_vs_reg): Node /soc@0/clocks/clkhyperlink0 has a reg or ranges property, but no unit name arch/arm/boot/dts/keystone-k2e-evm.dtb: Warning (unit_address_vs_reg): Node /soc@0/clocks/clkpcie1 has a reg or ranges property, but no unit name arch/arm/boot/dts/keystone-k2e-evm.dtb: Warning (unit_address_vs_reg): Node /soc@0/clocks/clkxge has a reg or ranges property, but no unit name Reported-by: Rob Herring <robh@kernel.org> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
75 lines
1.8 KiB
Plaintext
75 lines
1.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Keystone 2 Edison SoC specific device tree
|
|
*
|
|
* Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
|
|
*/
|
|
|
|
clocks {
|
|
mainpllclk: mainpllclk@2310110 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,keystone,main-pll-clock";
|
|
clocks = <&refclksys>;
|
|
reg = <0x02620350 4>, <0x02310110 4>, <0x02310108 4>;
|
|
reg-names = "control", "multiplier", "post-divider";
|
|
};
|
|
|
|
papllclk: papllclk@2620358 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,keystone,pll-clock";
|
|
clocks = <&refclkpass>;
|
|
clock-output-names = "papllclk";
|
|
reg = <0x02620358 4>;
|
|
reg-names = "control";
|
|
};
|
|
|
|
ddr3apllclk: ddr3apllclk@2620360 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,keystone,pll-clock";
|
|
clocks = <&refclkddr3a>;
|
|
clock-output-names = "ddr-3a-pll-clk";
|
|
reg = <0x02620360 4>;
|
|
reg-names = "control";
|
|
};
|
|
|
|
clkusb1: clkusb1@2350004 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,keystone,psc-clock";
|
|
clocks = <&chipclk16>;
|
|
clock-output-names = "usb1";
|
|
reg = <0x02350004 0xb00>, <0x02350000 0x400>;
|
|
reg-names = "control", "domain";
|
|
domain-id = <0>;
|
|
};
|
|
|
|
clkhyperlink0: clkhyperlink02350030 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,keystone,psc-clock";
|
|
clocks = <&chipclk12>;
|
|
clock-output-names = "hyperlink-0";
|
|
reg = <0x02350030 0xb00>, <0x02350014 0x400>;
|
|
reg-names = "control", "domain";
|
|
domain-id = <5>;
|
|
};
|
|
|
|
clkpcie1: clkpcie1@235006c {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,keystone,psc-clock";
|
|
clocks = <&chipclk12>;
|
|
clock-output-names = "pcie1";
|
|
reg = <0x0235006c 0xb00>, <0x02350048 0x400>;
|
|
reg-names = "control", "domain";
|
|
domain-id = <18>;
|
|
};
|
|
|
|
clkxge: clkxge@23500c8 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,keystone,psc-clock";
|
|
clocks = <&chipclk13>;
|
|
clock-output-names = "xge";
|
|
reg = <0x023500c8 0xb00>, <0x02350074 0x400>;
|
|
reg-names = "control", "domain";
|
|
domain-id = <29>;
|
|
};
|
|
};
|