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7dc37de7d5
Nand Flash Controller (NFC) can handle automatic transfers, sending the
commands and address cycles to the NAND Flash.
To use NFC in this driver, user needs to add NFC child node in nand flash
driver. The NFC child node includes NFC's compatible string and regiters
of the address and size of NFC command registers, NFC registers (embedded
in HSMC) and NFC SRAM.
Also user need to set up the HSMC irq, which use to check whether nfc
command is finish or not.
This driver has been tested on SAMA5D3X-EK board with JFFS2, YAFFS,
UBIFS and mtd-utils.
I put the part of the mtd_speedtest result here for your information.
>From the mtd_speedtest, we can see the NFC will reduce the %50 of cpu load
when writing nand flash. No change when reading.
In the meantime, the speed will be slow about %8.
- commands use to test:
#insmod /mnt/mtd_speedtest.ko dev=2 &
#top -n 30 -d 1 | grep speedtest
- test result:
Before the patch:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: MTD device size 41943040, eraseblock size 131072, page size 2048, count of eraseblocks 320, pages per eraseblock 64, OOB size 64
515 495 root R 1164 0% 93% insmod /mnt/mtd_speedtest.ko dev=2
515 495 root R 1164 0% 98% insmod /mnt/mtd_speedtest.ko dev=2
515 495 root R 1164 0% 99% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: eraseblock write speed is 5768 KiB/s
mtd_speedtest: testing eraseblock read speed
515 495 root R 1164 0% 92% insmod /mnt/mtd_speedtest.ko dev=2
515 495 root R 1164 0% 91% insmod /mnt/mtd_speedtest.ko dev=2
515 495 root R 1164 0% 94% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: eraseblock read speed is 5932 KiB/s
mtd_speedtest: testing page write speed
515 495 root R 1164 0% 94% insmod /mnt/mtd_speedtest.ko dev=2
515 495 root R 1164 0% 98% insmod /mnt/mtd_speedtest.ko dev=2
515 495 root R 1164 0% 98% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: page write speed is 5770 KiB/s
mtd_speedtest: testing page read speed
515 495 root R 1164 0% 91% insmod /mnt/mtd_speedtest.ko dev=2
515 495 root R 1164 0% 89% insmod /mnt/mtd_speedtest.ko dev=2
515 495 root R 1164 0% 91% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: page read speed is 5910 KiB/s
After the patch:
=================================================
mtd_speedtest: MTD device: 2
mtd_speedtest: MTD device size 41943040, eraseblock size 131072, page size 2048, count of eraseblocks 320, pages per eraseblock 64, OOB size 64
mtd_speedtest: testing eraseblock write speed
509 495 root D 1164 0% 49% insmod /mnt/mtd_speedtest.ko dev=2
509 495 root D 1164 0% 50% insmod /mnt/mtd_speedtest.ko dev=2
509 495 root D 1164 0% 47% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: eraseblock write speed is 5370 KiB/s
mtd_speedtest: testing eraseblock read speed
509 495 root R 1164 0% 92% insmod /mnt/mtd_speedtest.ko dev=2
509 495 root R 1164 0% 91% insmod /mnt/mtd_speedtest.ko dev=2
509 495 root R 1164 0% 95% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: eraseblock read speed is 5715 KiB/s
mtd_speedtest: testing page write speed
509 495 root D 1164 0% 48% insmod /mnt/mtd_speedtest.ko dev=2
509 495 root D 1164 0% 47% insmod /mnt/mtd_speedtest.ko dev=2
509 495 root D 1164 0% 50% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: page write speed is 5224 KiB/s
mtd_speedtest: testing page read speed
509 495 root R 1164 0% 89% insmod /mnt/mtd_speedtest.ko dev=2
509 495 root R 1164 0% 94% insmod /mnt/mtd_speedtest.ko dev=2
509 495 root R 1164 0% 93% insmod /mnt/mtd_speedtest.ko dev=2
mtd_speedtest: page read speed is 5641 KiB/s
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
99 lines
3.4 KiB
C
99 lines
3.4 KiB
C
/*
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* Atmel Nand Flash Controller (NFC) - System peripherals regsters.
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* Based on SAMA5D3 datasheet.
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*
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* © Copyright 2013 Atmel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef ATMEL_NAND_NFC_H
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#define ATMEL_NAND_NFC_H
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/*
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* HSMC NFC registers
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*/
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#define ATMEL_HSMC_NFC_CFG 0x00 /* NFC Configuration Register */
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#define NFC_CFG_PAGESIZE (7 << 0)
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#define NFC_CFG_PAGESIZE_512 (0 << 0)
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#define NFC_CFG_PAGESIZE_1024 (1 << 0)
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#define NFC_CFG_PAGESIZE_2048 (2 << 0)
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#define NFC_CFG_PAGESIZE_4096 (3 << 0)
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#define NFC_CFG_PAGESIZE_8192 (4 << 0)
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#define NFC_CFG_WSPARE (1 << 8)
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#define NFC_CFG_RSPARE (1 << 9)
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#define NFC_CFG_NFC_DTOCYC (0xf << 16)
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#define NFC_CFG_NFC_DTOMUL (0x7 << 20)
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#define NFC_CFG_NFC_SPARESIZE (0x7f << 24)
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#define NFC_CFG_NFC_SPARESIZE_BIT_POS 24
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#define ATMEL_HSMC_NFC_CTRL 0x04 /* NFC Control Register */
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#define NFC_CTRL_ENABLE (1 << 0)
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#define NFC_CTRL_DISABLE (1 << 1)
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#define ATMEL_HSMC_NFC_SR 0x08 /* NFC Status Register */
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#define NFC_SR_XFR_DONE (1 << 16)
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#define NFC_SR_CMD_DONE (1 << 17)
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#define NFC_SR_RB_EDGE (1 << 24)
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#define ATMEL_HSMC_NFC_IER 0x0c
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#define ATMEL_HSMC_NFC_IDR 0x10
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#define ATMEL_HSMC_NFC_IMR 0x14
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#define ATMEL_HSMC_NFC_CYCLE0 0x18 /* NFC Address Cycle Zero */
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#define ATMEL_HSMC_NFC_ADDR_CYCLE0 (0xff)
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#define ATMEL_HSMC_NFC_BANK 0x1c /* NFC Bank Register */
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#define ATMEL_HSMC_NFC_BANK0 (0 << 0)
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#define ATMEL_HSMC_NFC_BANK1 (1 << 0)
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#define nfc_writel(addr, reg, value) \
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writel((value), (addr) + ATMEL_HSMC_NFC_##reg)
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#define nfc_readl(addr, reg) \
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readl_relaxed((addr) + ATMEL_HSMC_NFC_##reg)
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/*
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* NFC Address Command definitions
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*/
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#define NFCADDR_CMD_CMD1 (0xff << 2) /* Command for Cycle 1 */
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#define NFCADDR_CMD_CMD1_BIT_POS 2
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#define NFCADDR_CMD_CMD2 (0xff << 10) /* Command for Cycle 2 */
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#define NFCADDR_CMD_CMD2_BIT_POS 10
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#define NFCADDR_CMD_VCMD2 (0x1 << 18) /* Valid Cycle 2 Command */
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#define NFCADDR_CMD_ACYCLE (0x7 << 19) /* Number of Address required */
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#define NFCADDR_CMD_ACYCLE_NONE (0x0 << 19)
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#define NFCADDR_CMD_ACYCLE_1 (0x1 << 19)
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#define NFCADDR_CMD_ACYCLE_2 (0x2 << 19)
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#define NFCADDR_CMD_ACYCLE_3 (0x3 << 19)
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#define NFCADDR_CMD_ACYCLE_4 (0x4 << 19)
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#define NFCADDR_CMD_ACYCLE_5 (0x5 << 19)
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#define NFCADDR_CMD_ACYCLE_BIT_POS 19
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#define NFCADDR_CMD_CSID (0x7 << 22) /* Chip Select Identifier */
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#define NFCADDR_CMD_CSID_0 (0x0 << 22)
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#define NFCADDR_CMD_CSID_1 (0x1 << 22)
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#define NFCADDR_CMD_CSID_2 (0x2 << 22)
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#define NFCADDR_CMD_CSID_3 (0x3 << 22)
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#define NFCADDR_CMD_CSID_4 (0x4 << 22)
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#define NFCADDR_CMD_CSID_5 (0x5 << 22)
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#define NFCADDR_CMD_CSID_6 (0x6 << 22)
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#define NFCADDR_CMD_CSID_7 (0x7 << 22)
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#define NFCADDR_CMD_DATAEN (0x1 << 25) /* Data Transfer Enable */
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#define NFCADDR_CMD_DATADIS (0x0 << 25) /* Data Transfer Disable */
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#define NFCADDR_CMD_NFCRD (0x0 << 26) /* NFC Read Enable */
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#define NFCADDR_CMD_NFCWR (0x1 << 26) /* NFC Write Enable */
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#define NFCADDR_CMD_NFCBUSY (0x1 << 27) /* NFC Busy */
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#define nfc_cmd_addr1234_writel(cmd, addr1234, nfc_base) \
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writel((addr1234), (cmd) + nfc_base)
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#define nfc_cmd_readl(bitstatus, nfc_base) \
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readl_relaxed((bitstatus) + nfc_base)
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#define NFC_TIME_OUT_MS 100
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#define NFC_SRAM_BANK1_OFFSET 0x1200
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#endif
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