mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-13 01:26:43 +07:00
38cf189fa1
nvxx_graph_isr is already taking care of it. In some cases this could've made you miss PGRAPH interrupts (e.g. when you were supposed to get several IRQs of the same kind in a row). Signed-off-by: Francisco Jerez <currojerez@riseup.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
1315 lines
36 KiB
C
1315 lines
36 KiB
C
/*
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* Copyright 2007 Stephane Marchesin
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_hw.h"
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#include "nouveau_util.h"
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static int nv04_graph_register(struct drm_device *dev);
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static void nv04_graph_isr(struct drm_device *dev);
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static uint32_t nv04_graph_ctx_regs[] = {
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0x0040053c,
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0x00400544,
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0x00400540,
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0x00400548,
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NV04_PGRAPH_CTX_SWITCH1,
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NV04_PGRAPH_CTX_SWITCH2,
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NV04_PGRAPH_CTX_SWITCH3,
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NV04_PGRAPH_CTX_SWITCH4,
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NV04_PGRAPH_CTX_CACHE1,
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NV04_PGRAPH_CTX_CACHE2,
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NV04_PGRAPH_CTX_CACHE3,
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NV04_PGRAPH_CTX_CACHE4,
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0x00400184,
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0x004001a4,
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0x004001c4,
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0x004001e4,
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0x00400188,
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0x004001a8,
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0x004001c8,
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0x004001e8,
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0x0040018c,
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0x004001ac,
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0x004001cc,
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0x004001ec,
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0x00400190,
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0x004001b0,
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0x004001d0,
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0x004001f0,
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0x00400194,
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0x004001b4,
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0x004001d4,
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0x004001f4,
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0x00400198,
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0x004001b8,
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0x004001d8,
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0x004001f8,
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0x0040019c,
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0x004001bc,
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0x004001dc,
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0x004001fc,
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0x00400174,
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NV04_PGRAPH_DMA_START_0,
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NV04_PGRAPH_DMA_START_1,
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NV04_PGRAPH_DMA_LENGTH,
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NV04_PGRAPH_DMA_MISC,
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NV04_PGRAPH_DMA_PITCH,
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NV04_PGRAPH_BOFFSET0,
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NV04_PGRAPH_BBASE0,
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NV04_PGRAPH_BLIMIT0,
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NV04_PGRAPH_BOFFSET1,
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NV04_PGRAPH_BBASE1,
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NV04_PGRAPH_BLIMIT1,
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NV04_PGRAPH_BOFFSET2,
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NV04_PGRAPH_BBASE2,
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NV04_PGRAPH_BLIMIT2,
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NV04_PGRAPH_BOFFSET3,
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NV04_PGRAPH_BBASE3,
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NV04_PGRAPH_BLIMIT3,
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NV04_PGRAPH_BOFFSET4,
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NV04_PGRAPH_BBASE4,
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NV04_PGRAPH_BLIMIT4,
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NV04_PGRAPH_BOFFSET5,
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NV04_PGRAPH_BBASE5,
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NV04_PGRAPH_BLIMIT5,
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NV04_PGRAPH_BPITCH0,
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NV04_PGRAPH_BPITCH1,
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NV04_PGRAPH_BPITCH2,
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NV04_PGRAPH_BPITCH3,
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NV04_PGRAPH_BPITCH4,
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NV04_PGRAPH_SURFACE,
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NV04_PGRAPH_STATE,
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NV04_PGRAPH_BSWIZZLE2,
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NV04_PGRAPH_BSWIZZLE5,
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NV04_PGRAPH_BPIXEL,
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NV04_PGRAPH_NOTIFY,
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NV04_PGRAPH_PATT_COLOR0,
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NV04_PGRAPH_PATT_COLOR1,
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NV04_PGRAPH_PATT_COLORRAM+0x00,
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NV04_PGRAPH_PATT_COLORRAM+0x04,
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NV04_PGRAPH_PATT_COLORRAM+0x08,
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NV04_PGRAPH_PATT_COLORRAM+0x0c,
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NV04_PGRAPH_PATT_COLORRAM+0x10,
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NV04_PGRAPH_PATT_COLORRAM+0x14,
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NV04_PGRAPH_PATT_COLORRAM+0x18,
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NV04_PGRAPH_PATT_COLORRAM+0x1c,
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NV04_PGRAPH_PATT_COLORRAM+0x20,
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NV04_PGRAPH_PATT_COLORRAM+0x24,
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NV04_PGRAPH_PATT_COLORRAM+0x28,
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NV04_PGRAPH_PATT_COLORRAM+0x2c,
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NV04_PGRAPH_PATT_COLORRAM+0x30,
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NV04_PGRAPH_PATT_COLORRAM+0x34,
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NV04_PGRAPH_PATT_COLORRAM+0x38,
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NV04_PGRAPH_PATT_COLORRAM+0x3c,
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NV04_PGRAPH_PATT_COLORRAM+0x40,
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NV04_PGRAPH_PATT_COLORRAM+0x44,
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NV04_PGRAPH_PATT_COLORRAM+0x48,
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NV04_PGRAPH_PATT_COLORRAM+0x4c,
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NV04_PGRAPH_PATT_COLORRAM+0x50,
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NV04_PGRAPH_PATT_COLORRAM+0x54,
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NV04_PGRAPH_PATT_COLORRAM+0x58,
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NV04_PGRAPH_PATT_COLORRAM+0x5c,
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NV04_PGRAPH_PATT_COLORRAM+0x60,
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NV04_PGRAPH_PATT_COLORRAM+0x64,
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NV04_PGRAPH_PATT_COLORRAM+0x68,
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NV04_PGRAPH_PATT_COLORRAM+0x6c,
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NV04_PGRAPH_PATT_COLORRAM+0x70,
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NV04_PGRAPH_PATT_COLORRAM+0x74,
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NV04_PGRAPH_PATT_COLORRAM+0x78,
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NV04_PGRAPH_PATT_COLORRAM+0x7c,
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NV04_PGRAPH_PATT_COLORRAM+0x80,
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NV04_PGRAPH_PATT_COLORRAM+0x84,
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NV04_PGRAPH_PATT_COLORRAM+0x88,
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NV04_PGRAPH_PATT_COLORRAM+0x8c,
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NV04_PGRAPH_PATT_COLORRAM+0x90,
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NV04_PGRAPH_PATT_COLORRAM+0x94,
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NV04_PGRAPH_PATT_COLORRAM+0x98,
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NV04_PGRAPH_PATT_COLORRAM+0x9c,
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NV04_PGRAPH_PATT_COLORRAM+0xa0,
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NV04_PGRAPH_PATT_COLORRAM+0xa4,
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NV04_PGRAPH_PATT_COLORRAM+0xa8,
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NV04_PGRAPH_PATT_COLORRAM+0xac,
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NV04_PGRAPH_PATT_COLORRAM+0xb0,
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NV04_PGRAPH_PATT_COLORRAM+0xb4,
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NV04_PGRAPH_PATT_COLORRAM+0xb8,
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NV04_PGRAPH_PATT_COLORRAM+0xbc,
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NV04_PGRAPH_PATT_COLORRAM+0xc0,
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NV04_PGRAPH_PATT_COLORRAM+0xc4,
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NV04_PGRAPH_PATT_COLORRAM+0xc8,
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NV04_PGRAPH_PATT_COLORRAM+0xcc,
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NV04_PGRAPH_PATT_COLORRAM+0xd0,
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NV04_PGRAPH_PATT_COLORRAM+0xd4,
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NV04_PGRAPH_PATT_COLORRAM+0xd8,
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NV04_PGRAPH_PATT_COLORRAM+0xdc,
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NV04_PGRAPH_PATT_COLORRAM+0xe0,
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NV04_PGRAPH_PATT_COLORRAM+0xe4,
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NV04_PGRAPH_PATT_COLORRAM+0xe8,
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NV04_PGRAPH_PATT_COLORRAM+0xec,
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NV04_PGRAPH_PATT_COLORRAM+0xf0,
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NV04_PGRAPH_PATT_COLORRAM+0xf4,
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NV04_PGRAPH_PATT_COLORRAM+0xf8,
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NV04_PGRAPH_PATT_COLORRAM+0xfc,
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NV04_PGRAPH_PATTERN,
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0x0040080c,
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NV04_PGRAPH_PATTERN_SHAPE,
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0x00400600,
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NV04_PGRAPH_ROP3,
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NV04_PGRAPH_CHROMA,
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NV04_PGRAPH_BETA_AND,
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NV04_PGRAPH_BETA_PREMULT,
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NV04_PGRAPH_CONTROL0,
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NV04_PGRAPH_CONTROL1,
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NV04_PGRAPH_CONTROL2,
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NV04_PGRAPH_BLEND,
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NV04_PGRAPH_STORED_FMT,
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NV04_PGRAPH_SOURCE_COLOR,
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0x00400560,
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0x00400568,
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0x00400564,
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0x0040056c,
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0x00400400,
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0x00400480,
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0x00400404,
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0x00400484,
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0x00400408,
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0x00400488,
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0x0040040c,
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0x0040048c,
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0x00400410,
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0x00400490,
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0x00400414,
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0x00400494,
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0x00400418,
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0x00400498,
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0x0040041c,
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0x0040049c,
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0x00400420,
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0x004004a0,
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0x00400424,
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0x004004a4,
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0x00400428,
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0x004004a8,
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0x0040042c,
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0x004004ac,
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0x00400430,
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0x004004b0,
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0x00400434,
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0x004004b4,
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0x00400438,
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0x004004b8,
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0x0040043c,
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0x004004bc,
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0x00400440,
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0x004004c0,
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0x00400444,
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0x004004c4,
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0x00400448,
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0x004004c8,
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0x0040044c,
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0x004004cc,
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0x00400450,
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0x004004d0,
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0x00400454,
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0x004004d4,
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0x00400458,
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0x004004d8,
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0x0040045c,
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0x004004dc,
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0x00400460,
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0x004004e0,
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0x00400464,
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0x004004e4,
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0x00400468,
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0x004004e8,
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0x0040046c,
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0x004004ec,
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0x00400470,
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0x004004f0,
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0x00400474,
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0x004004f4,
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0x00400478,
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0x004004f8,
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0x0040047c,
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0x004004fc,
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0x00400534,
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0x00400538,
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0x00400514,
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0x00400518,
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0x0040051c,
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0x00400520,
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0x00400524,
|
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0x00400528,
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0x0040052c,
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0x00400530,
|
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0x00400d00,
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0x00400d40,
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0x00400d80,
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0x00400d04,
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0x00400d44,
|
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0x00400d84,
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0x00400d08,
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0x00400d48,
|
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0x00400d88,
|
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0x00400d0c,
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0x00400d4c,
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0x00400d8c,
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0x00400d10,
|
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0x00400d50,
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0x00400d90,
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0x00400d14,
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0x00400d54,
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0x00400d94,
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0x00400d18,
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0x00400d58,
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0x00400d98,
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0x00400d1c,
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0x00400d5c,
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0x00400d9c,
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0x00400d20,
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0x00400d60,
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0x00400da0,
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0x00400d24,
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0x00400d64,
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0x00400da4,
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0x00400d28,
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0x00400d68,
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0x00400da8,
|
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0x00400d2c,
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0x00400d6c,
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0x00400dac,
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0x00400d30,
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0x00400d70,
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0x00400db0,
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0x00400d34,
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0x00400d74,
|
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0x00400db4,
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0x00400d38,
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0x00400d78,
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0x00400db8,
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0x00400d3c,
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0x00400d7c,
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0x00400dbc,
|
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0x00400590,
|
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0x00400594,
|
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0x00400598,
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0x0040059c,
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0x004005a8,
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0x004005ac,
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0x004005b0,
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0x004005b4,
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0x004005c0,
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0x004005c4,
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0x004005c8,
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0x004005cc,
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0x004005d0,
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0x004005d4,
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0x004005d8,
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0x004005dc,
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0x004005e0,
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NV04_PGRAPH_PASSTHRU_0,
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NV04_PGRAPH_PASSTHRU_1,
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NV04_PGRAPH_PASSTHRU_2,
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NV04_PGRAPH_DVD_COLORFMT,
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NV04_PGRAPH_SCALED_FORMAT,
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NV04_PGRAPH_MISC24_0,
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NV04_PGRAPH_MISC24_1,
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NV04_PGRAPH_MISC24_2,
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0x00400500,
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0x00400504,
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NV04_PGRAPH_VALID1,
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NV04_PGRAPH_VALID2,
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NV04_PGRAPH_DEBUG_3
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};
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struct graph_state {
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uint32_t nv04[ARRAY_SIZE(nv04_graph_ctx_regs)];
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};
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struct nouveau_channel *
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nv04_graph_channel(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int chid = dev_priv->engine.fifo.channels;
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if (nv_rd32(dev, NV04_PGRAPH_CTX_CONTROL) & 0x00010000)
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chid = nv_rd32(dev, NV04_PGRAPH_CTX_USER) >> 24;
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if (chid >= dev_priv->engine.fifo.channels)
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return NULL;
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return dev_priv->channels.ptr[chid];
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}
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static void
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nv04_graph_context_switch(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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struct nouveau_channel *chan = NULL;
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int chid;
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nouveau_wait_for_idle(dev);
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|
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/* If previous context is valid, we need to save it */
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pgraph->unload_context(dev);
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|
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/* Load context for next channel */
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chid = dev_priv->engine.fifo.channel_id(dev);
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chan = dev_priv->channels.ptr[chid];
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if (chan)
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nv04_graph_load_context(chan);
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}
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|
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static uint32_t *ctx_reg(struct graph_state *ctx, uint32_t reg)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++) {
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if (nv04_graph_ctx_regs[i] == reg)
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return &ctx->nv04[i];
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}
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|
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return NULL;
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}
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|
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int nv04_graph_create_context(struct nouveau_channel *chan)
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{
|
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struct graph_state *pgraph_ctx;
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NV_DEBUG(chan->dev, "nv04_graph_context_create %d\n", chan->id);
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|
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chan->pgraph_ctx = pgraph_ctx = kzalloc(sizeof(*pgraph_ctx),
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GFP_KERNEL);
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if (pgraph_ctx == NULL)
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return -ENOMEM;
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*ctx_reg(pgraph_ctx, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31;
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|
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return 0;
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}
|
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|
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void nv04_graph_destroy_context(struct nouveau_channel *chan)
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{
|
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struct drm_device *dev = chan->dev;
|
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struct drm_nouveau_private *dev_priv = dev->dev_private;
|
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struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
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struct graph_state *pgraph_ctx = chan->pgraph_ctx;
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unsigned long flags;
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|
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spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
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pgraph->fifo_access(dev, false);
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|
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/* Unload the context if it's the currently active one */
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if (pgraph->channel(dev) == chan)
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pgraph->unload_context(dev);
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|
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/* Free the context resources */
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kfree(pgraph_ctx);
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chan->pgraph_ctx = NULL;
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pgraph->fifo_access(dev, true);
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spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
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}
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|
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int nv04_graph_load_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct graph_state *pgraph_ctx = chan->pgraph_ctx;
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uint32_t tmp;
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int i;
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|
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for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++)
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nv_wr32(dev, nv04_graph_ctx_regs[i], pgraph_ctx->nv04[i]);
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nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10010100);
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tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
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nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp | chan->id << 24);
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tmp = nv_rd32(dev, NV04_PGRAPH_FFINTFC_ST2);
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nv_wr32(dev, NV04_PGRAPH_FFINTFC_ST2, tmp & 0x000fffff);
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|
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return 0;
|
|
}
|
|
|
|
int
|
|
nv04_graph_unload_context(struct drm_device *dev)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
|
|
struct nouveau_channel *chan = NULL;
|
|
struct graph_state *ctx;
|
|
uint32_t tmp;
|
|
int i;
|
|
|
|
chan = pgraph->channel(dev);
|
|
if (!chan)
|
|
return 0;
|
|
ctx = chan->pgraph_ctx;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++)
|
|
ctx->nv04[i] = nv_rd32(dev, nv04_graph_ctx_regs[i]);
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL, 0x10000000);
|
|
tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
|
|
tmp |= (dev_priv->engine.fifo.channels - 1) << 24;
|
|
nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp);
|
|
return 0;
|
|
}
|
|
|
|
int nv04_graph_init(struct drm_device *dev)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
uint32_t tmp;
|
|
int ret;
|
|
|
|
nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
|
|
~NV_PMC_ENABLE_PGRAPH);
|
|
nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
|
|
NV_PMC_ENABLE_PGRAPH);
|
|
|
|
ret = nv04_graph_register(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Enable PGRAPH interrupts */
|
|
nouveau_irq_register(dev, 12, nv04_graph_isr);
|
|
nv_wr32(dev, NV03_PGRAPH_INTR, 0xFFFFFFFF);
|
|
nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_VALID1, 0);
|
|
nv_wr32(dev, NV04_PGRAPH_VALID2, 0);
|
|
/*nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x000001FF);
|
|
nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/
|
|
nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x1231c000);
|
|
/*1231C000 blob, 001 haiku*/
|
|
//*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/
|
|
nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x72111100);
|
|
/*0x72111100 blob , 01 haiku*/
|
|
/*nv_wr32(dev, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/
|
|
nv_wr32(dev, NV04_PGRAPH_DEBUG_2, 0x11d5f071);
|
|
/*haiku same*/
|
|
|
|
/*nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xfad4ff31);*/
|
|
nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xf0d4ff31);
|
|
/*haiku and blob 10d4*/
|
|
|
|
nv_wr32(dev, NV04_PGRAPH_STATE , 0xFFFFFFFF);
|
|
nv_wr32(dev, NV04_PGRAPH_CTX_CONTROL , 0x10000100);
|
|
tmp = nv_rd32(dev, NV04_PGRAPH_CTX_USER) & 0x00ffffff;
|
|
tmp |= (dev_priv->engine.fifo.channels - 1) << 24;
|
|
nv_wr32(dev, NV04_PGRAPH_CTX_USER, tmp);
|
|
|
|
/* These don't belong here, they're part of a per-channel context */
|
|
nv_wr32(dev, NV04_PGRAPH_PATTERN_SHAPE, 0x00000000);
|
|
nv_wr32(dev, NV04_PGRAPH_BETA_AND , 0xFFFFFFFF);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void nv04_graph_takedown(struct drm_device *dev)
|
|
{
|
|
nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
|
|
nouveau_irq_unregister(dev, 12);
|
|
}
|
|
|
|
void
|
|
nv04_graph_fifo_access(struct drm_device *dev, bool enabled)
|
|
{
|
|
if (enabled)
|
|
nv_wr32(dev, NV04_PGRAPH_FIFO,
|
|
nv_rd32(dev, NV04_PGRAPH_FIFO) | 1);
|
|
else
|
|
nv_wr32(dev, NV04_PGRAPH_FIFO,
|
|
nv_rd32(dev, NV04_PGRAPH_FIFO) & ~1);
|
|
}
|
|
|
|
static int
|
|
nv04_graph_mthd_set_ref(struct nouveau_channel *chan,
|
|
u32 class, u32 mthd, u32 data)
|
|
{
|
|
atomic_set(&chan->fence.last_sequence_irq, data);
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
|
|
u32 class, u32 mthd, u32 data)
|
|
{
|
|
struct drm_device *dev = chan->dev;
|
|
struct nouveau_page_flip_state s;
|
|
|
|
if (!nouveau_finish_page_flip(chan, &s))
|
|
nv_set_crtc_base(dev, s.crtc,
|
|
s.offset + s.y * s.pitch + s.x * s.bpp / 8);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Software methods, why they are needed, and how they all work:
|
|
*
|
|
* NV04 and NV05 keep most of the state in PGRAPH context itself, but some
|
|
* 2d engine settings are kept inside the grobjs themselves. The grobjs are
|
|
* 3 words long on both. grobj format on NV04 is:
|
|
*
|
|
* word 0:
|
|
* - bits 0-7: class
|
|
* - bit 12: color key active
|
|
* - bit 13: clip rect active
|
|
* - bit 14: if set, destination surface is swizzled and taken from buffer 5
|
|
* [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken
|
|
* from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or
|
|
* NV03_CONTEXT_SURFACE_DST].
|
|
* - bits 15-17: 2d operation [aka patch config]
|
|
* - bit 24: patch valid [enables rendering using this object]
|
|
* - bit 25: surf3d valid [for tex_tri and multitex_tri only]
|
|
* word 1:
|
|
* - bits 0-1: mono format
|
|
* - bits 8-13: color format
|
|
* - bits 16-31: DMA_NOTIFY instance
|
|
* word 2:
|
|
* - bits 0-15: DMA_A instance
|
|
* - bits 16-31: DMA_B instance
|
|
*
|
|
* On NV05 it's:
|
|
*
|
|
* word 0:
|
|
* - bits 0-7: class
|
|
* - bit 12: color key active
|
|
* - bit 13: clip rect active
|
|
* - bit 14: if set, destination surface is swizzled and taken from buffer 5
|
|
* [set by NV04_SWIZZLED_SURFACE], otherwise it's linear and taken
|
|
* from buffer 0 [set by NV04_CONTEXT_SURFACES_2D or
|
|
* NV03_CONTEXT_SURFACE_DST].
|
|
* - bits 15-17: 2d operation [aka patch config]
|
|
* - bits 20-22: dither mode
|
|
* - bit 24: patch valid [enables rendering using this object]
|
|
* - bit 25: surface_dst/surface_color/surf2d/surf3d valid
|
|
* - bit 26: surface_src/surface_zeta valid
|
|
* - bit 27: pattern valid
|
|
* - bit 28: rop valid
|
|
* - bit 29: beta1 valid
|
|
* - bit 30: beta4 valid
|
|
* word 1:
|
|
* - bits 0-1: mono format
|
|
* - bits 8-13: color format
|
|
* - bits 16-31: DMA_NOTIFY instance
|
|
* word 2:
|
|
* - bits 0-15: DMA_A instance
|
|
* - bits 16-31: DMA_B instance
|
|
*
|
|
* NV05 will set/unset the relevant valid bits when you poke the relevant
|
|
* object-binding methods with object of the proper type, or with the NULL
|
|
* type. It'll only allow rendering using the grobj if all needed objects
|
|
* are bound. The needed set of objects depends on selected operation: for
|
|
* example rop object is needed by ROP_AND, but not by SRCCOPY_AND.
|
|
*
|
|
* NV04 doesn't have these methods implemented at all, and doesn't have the
|
|
* relevant bits in grobj. Instead, it'll allow rendering whenever bit 24
|
|
* is set. So we have to emulate them in software, internally keeping the
|
|
* same bits as NV05 does. Since grobjs are aligned to 16 bytes on nv04,
|
|
* but the last word isn't actually used for anything, we abuse it for this
|
|
* purpose.
|
|
*
|
|
* Actually, NV05 can optionally check bit 24 too, but we disable this since
|
|
* there's no use for it.
|
|
*
|
|
* For unknown reasons, NV04 implements surf3d binding in hardware as an
|
|
* exception. Also for unknown reasons, NV04 doesn't implement the clipping
|
|
* methods on the surf3d object, so we have to emulate them too.
|
|
*/
|
|
|
|
static void
|
|
nv04_graph_set_ctx1(struct nouveau_channel *chan, u32 mask, u32 value)
|
|
{
|
|
struct drm_device *dev = chan->dev;
|
|
u32 instance = (nv_rd32(dev, NV04_PGRAPH_CTX_SWITCH4) & 0xffff) << 4;
|
|
int subc = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 13) & 0x7;
|
|
u32 tmp;
|
|
|
|
tmp = nv_ri32(dev, instance);
|
|
tmp &= ~mask;
|
|
tmp |= value;
|
|
|
|
nv_wi32(dev, instance, tmp);
|
|
nv_wr32(dev, NV04_PGRAPH_CTX_SWITCH1, tmp);
|
|
nv_wr32(dev, NV04_PGRAPH_CTX_CACHE1 + (subc<<2), tmp);
|
|
}
|
|
|
|
static void
|
|
nv04_graph_set_ctx_val(struct nouveau_channel *chan, u32 mask, u32 value)
|
|
{
|
|
struct drm_device *dev = chan->dev;
|
|
u32 instance = (nv_rd32(dev, NV04_PGRAPH_CTX_SWITCH4) & 0xffff) << 4;
|
|
u32 tmp, ctx1;
|
|
int class, op, valid = 1;
|
|
|
|
ctx1 = nv_ri32(dev, instance);
|
|
class = ctx1 & 0xff;
|
|
op = (ctx1 >> 15) & 7;
|
|
tmp = nv_ri32(dev, instance + 0xc);
|
|
tmp &= ~mask;
|
|
tmp |= value;
|
|
nv_wi32(dev, instance + 0xc, tmp);
|
|
|
|
/* check for valid surf2d/surf_dst/surf_color */
|
|
if (!(tmp & 0x02000000))
|
|
valid = 0;
|
|
/* check for valid surf_src/surf_zeta */
|
|
if ((class == 0x1f || class == 0x48) && !(tmp & 0x04000000))
|
|
valid = 0;
|
|
|
|
switch (op) {
|
|
/* SRCCOPY_AND, SRCCOPY: no extra objects required */
|
|
case 0:
|
|
case 3:
|
|
break;
|
|
/* ROP_AND: requires pattern and rop */
|
|
case 1:
|
|
if (!(tmp & 0x18000000))
|
|
valid = 0;
|
|
break;
|
|
/* BLEND_AND: requires beta1 */
|
|
case 2:
|
|
if (!(tmp & 0x20000000))
|
|
valid = 0;
|
|
break;
|
|
/* SRCCOPY_PREMULT, BLEND_PREMULT: beta4 required */
|
|
case 4:
|
|
case 5:
|
|
if (!(tmp & 0x40000000))
|
|
valid = 0;
|
|
break;
|
|
}
|
|
|
|
nv04_graph_set_ctx1(chan, 0x01000000, valid << 24);
|
|
}
|
|
|
|
static int
|
|
nv04_graph_mthd_set_operation(struct nouveau_channel *chan,
|
|
u32 class, u32 mthd, u32 data)
|
|
{
|
|
if (data > 5)
|
|
return 1;
|
|
/* Old versions of the objects only accept first three operations. */
|
|
if (data > 2 && class < 0x40)
|
|
return 1;
|
|
nv04_graph_set_ctx1(chan, 0x00038000, data << 15);
|
|
/* changing operation changes set of objects needed for validation */
|
|
nv04_graph_set_ctx_val(chan, 0, 0);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nv04_graph_mthd_surf3d_clip_h(struct nouveau_channel *chan,
|
|
u32 class, u32 mthd, u32 data)
|
|
{
|
|
uint32_t min = data & 0xffff, max;
|
|
uint32_t w = data >> 16;
|
|
if (min & 0x8000)
|
|
/* too large */
|
|
return 1;
|
|
if (w & 0x8000)
|
|
/* yes, it accepts negative for some reason. */
|
|
w |= 0xffff0000;
|
|
max = min + w;
|
|
max &= 0x3ffff;
|
|
nv_wr32(chan->dev, 0x40053c, min);
|
|
nv_wr32(chan->dev, 0x400544, max);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nv04_graph_mthd_surf3d_clip_v(struct nouveau_channel *chan,
|
|
u32 class, u32 mthd, u32 data)
|
|
{
|
|
uint32_t min = data & 0xffff, max;
|
|
uint32_t w = data >> 16;
|
|
if (min & 0x8000)
|
|
/* too large */
|
|
return 1;
|
|
if (w & 0x8000)
|
|
/* yes, it accepts negative for some reason. */
|
|
w |= 0xffff0000;
|
|
max = min + w;
|
|
max &= 0x3ffff;
|
|
nv_wr32(chan->dev, 0x400540, min);
|
|
nv_wr32(chan->dev, 0x400548, max);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nv04_graph_mthd_bind_surf2d(struct nouveau_channel *chan,
|
|
u32 class, u32 mthd, u32 data)
|
|
{
|
|
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
|
|
case 0x30:
|
|
nv04_graph_set_ctx1(chan, 0x00004000, 0);
|
|
nv04_graph_set_ctx_val(chan, 0x02000000, 0);
|
|
return 0;
|
|
case 0x42:
|
|
nv04_graph_set_ctx1(chan, 0x00004000, 0);
|
|
nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
|
|
return 0;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static int
|
|
nv04_graph_mthd_bind_surf2d_swzsurf(struct nouveau_channel *chan,
|
|
u32 class, u32 mthd, u32 data)
|
|
{
|
|
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
|
|
case 0x30:
|
|
nv04_graph_set_ctx1(chan, 0x00004000, 0);
|
|
nv04_graph_set_ctx_val(chan, 0x02000000, 0);
|
|
return 0;
|
|
case 0x42:
|
|
nv04_graph_set_ctx1(chan, 0x00004000, 0);
|
|
nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
|
|
return 0;
|
|
case 0x52:
|
|
nv04_graph_set_ctx1(chan, 0x00004000, 0x00004000);
|
|
nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
|
|
return 0;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static int
|
|
nv04_graph_mthd_bind_nv01_patt(struct nouveau_channel *chan,
|
|
u32 class, u32 mthd, u32 data)
|
|
{
|
|
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
|
|
case 0x30:
|
|
nv04_graph_set_ctx_val(chan, 0x08000000, 0);
|
|
return 0;
|
|
case 0x18:
|
|
nv04_graph_set_ctx_val(chan, 0x08000000, 0x08000000);
|
|
return 0;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static int
|
|
nv04_graph_mthd_bind_nv04_patt(struct nouveau_channel *chan,
|
|
u32 class, u32 mthd, u32 data)
|
|
{
|
|
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
|
|
case 0x30:
|
|
nv04_graph_set_ctx_val(chan, 0x08000000, 0);
|
|
return 0;
|
|
case 0x44:
|
|
nv04_graph_set_ctx_val(chan, 0x08000000, 0x08000000);
|
|
return 0;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static int
|
|
nv04_graph_mthd_bind_rop(struct nouveau_channel *chan,
|
|
u32 class, u32 mthd, u32 data)
|
|
{
|
|
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
|
|
case 0x30:
|
|
nv04_graph_set_ctx_val(chan, 0x10000000, 0);
|
|
return 0;
|
|
case 0x43:
|
|
nv04_graph_set_ctx_val(chan, 0x10000000, 0x10000000);
|
|
return 0;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static int
|
|
nv04_graph_mthd_bind_beta1(struct nouveau_channel *chan,
|
|
u32 class, u32 mthd, u32 data)
|
|
{
|
|
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
|
|
case 0x30:
|
|
nv04_graph_set_ctx_val(chan, 0x20000000, 0);
|
|
return 0;
|
|
case 0x12:
|
|
nv04_graph_set_ctx_val(chan, 0x20000000, 0x20000000);
|
|
return 0;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static int
|
|
nv04_graph_mthd_bind_beta4(struct nouveau_channel *chan,
|
|
u32 class, u32 mthd, u32 data)
|
|
{
|
|
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
|
|
case 0x30:
|
|
nv04_graph_set_ctx_val(chan, 0x40000000, 0);
|
|
return 0;
|
|
case 0x72:
|
|
nv04_graph_set_ctx_val(chan, 0x40000000, 0x40000000);
|
|
return 0;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static int
|
|
nv04_graph_mthd_bind_surf_dst(struct nouveau_channel *chan,
|
|
u32 class, u32 mthd, u32 data)
|
|
{
|
|
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
|
|
case 0x30:
|
|
nv04_graph_set_ctx_val(chan, 0x02000000, 0);
|
|
return 0;
|
|
case 0x58:
|
|
nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
|
|
return 0;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static int
|
|
nv04_graph_mthd_bind_surf_src(struct nouveau_channel *chan,
|
|
u32 class, u32 mthd, u32 data)
|
|
{
|
|
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
|
|
case 0x30:
|
|
nv04_graph_set_ctx_val(chan, 0x04000000, 0);
|
|
return 0;
|
|
case 0x59:
|
|
nv04_graph_set_ctx_val(chan, 0x04000000, 0x04000000);
|
|
return 0;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static int
|
|
nv04_graph_mthd_bind_surf_color(struct nouveau_channel *chan,
|
|
u32 class, u32 mthd, u32 data)
|
|
{
|
|
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
|
|
case 0x30:
|
|
nv04_graph_set_ctx_val(chan, 0x02000000, 0);
|
|
return 0;
|
|
case 0x5a:
|
|
nv04_graph_set_ctx_val(chan, 0x02000000, 0x02000000);
|
|
return 0;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static int
|
|
nv04_graph_mthd_bind_surf_zeta(struct nouveau_channel *chan,
|
|
u32 class, u32 mthd, u32 data)
|
|
{
|
|
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
|
|
case 0x30:
|
|
nv04_graph_set_ctx_val(chan, 0x04000000, 0);
|
|
return 0;
|
|
case 0x5b:
|
|
nv04_graph_set_ctx_val(chan, 0x04000000, 0x04000000);
|
|
return 0;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static int
|
|
nv04_graph_mthd_bind_clip(struct nouveau_channel *chan,
|
|
u32 class, u32 mthd, u32 data)
|
|
{
|
|
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
|
|
case 0x30:
|
|
nv04_graph_set_ctx1(chan, 0x2000, 0);
|
|
return 0;
|
|
case 0x19:
|
|
nv04_graph_set_ctx1(chan, 0x2000, 0x2000);
|
|
return 0;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static int
|
|
nv04_graph_mthd_bind_chroma(struct nouveau_channel *chan,
|
|
u32 class, u32 mthd, u32 data)
|
|
{
|
|
switch (nv_ri32(chan->dev, data << 4) & 0xff) {
|
|
case 0x30:
|
|
nv04_graph_set_ctx1(chan, 0x1000, 0);
|
|
return 0;
|
|
/* Yes, for some reason even the old versions of objects
|
|
* accept 0x57 and not 0x17. Consistency be damned.
|
|
*/
|
|
case 0x57:
|
|
nv04_graph_set_ctx1(chan, 0x1000, 0x1000);
|
|
return 0;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
static int
|
|
nv04_graph_register(struct drm_device *dev)
|
|
{
|
|
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
|
|
|
if (dev_priv->engine.graph.registered)
|
|
return 0;
|
|
|
|
/* dvd subpicture */
|
|
NVOBJ_CLASS(dev, 0x0038, GR);
|
|
|
|
/* m2mf */
|
|
NVOBJ_CLASS(dev, 0x0039, GR);
|
|
|
|
/* nv03 gdirect */
|
|
NVOBJ_CLASS(dev, 0x004b, GR);
|
|
NVOBJ_MTHD (dev, 0x004b, 0x0184, nv04_graph_mthd_bind_nv01_patt);
|
|
NVOBJ_MTHD (dev, 0x004b, 0x0188, nv04_graph_mthd_bind_rop);
|
|
NVOBJ_MTHD (dev, 0x004b, 0x018c, nv04_graph_mthd_bind_beta1);
|
|
NVOBJ_MTHD (dev, 0x004b, 0x0190, nv04_graph_mthd_bind_surf_dst);
|
|
NVOBJ_MTHD (dev, 0x004b, 0x02fc, nv04_graph_mthd_set_operation);
|
|
|
|
/* nv04 gdirect */
|
|
NVOBJ_CLASS(dev, 0x004a, GR);
|
|
NVOBJ_MTHD (dev, 0x004a, 0x0188, nv04_graph_mthd_bind_nv04_patt);
|
|
NVOBJ_MTHD (dev, 0x004a, 0x018c, nv04_graph_mthd_bind_rop);
|
|
NVOBJ_MTHD (dev, 0x004a, 0x0190, nv04_graph_mthd_bind_beta1);
|
|
NVOBJ_MTHD (dev, 0x004a, 0x0194, nv04_graph_mthd_bind_beta4);
|
|
NVOBJ_MTHD (dev, 0x004a, 0x0198, nv04_graph_mthd_bind_surf2d);
|
|
NVOBJ_MTHD (dev, 0x004a, 0x02fc, nv04_graph_mthd_set_operation);
|
|
|
|
/* nv01 imageblit */
|
|
NVOBJ_CLASS(dev, 0x001f, GR);
|
|
NVOBJ_MTHD (dev, 0x001f, 0x0184, nv04_graph_mthd_bind_chroma);
|
|
NVOBJ_MTHD (dev, 0x001f, 0x0188, nv04_graph_mthd_bind_clip);
|
|
NVOBJ_MTHD (dev, 0x001f, 0x018c, nv04_graph_mthd_bind_nv01_patt);
|
|
NVOBJ_MTHD (dev, 0x001f, 0x0190, nv04_graph_mthd_bind_rop);
|
|
NVOBJ_MTHD (dev, 0x001f, 0x0194, nv04_graph_mthd_bind_beta1);
|
|
NVOBJ_MTHD (dev, 0x001f, 0x0198, nv04_graph_mthd_bind_surf_dst);
|
|
NVOBJ_MTHD (dev, 0x001f, 0x019c, nv04_graph_mthd_bind_surf_src);
|
|
NVOBJ_MTHD (dev, 0x001f, 0x02fc, nv04_graph_mthd_set_operation);
|
|
|
|
/* nv04 imageblit */
|
|
NVOBJ_CLASS(dev, 0x005f, GR);
|
|
NVOBJ_MTHD (dev, 0x005f, 0x0184, nv04_graph_mthd_bind_chroma);
|
|
NVOBJ_MTHD (dev, 0x005f, 0x0188, nv04_graph_mthd_bind_clip);
|
|
NVOBJ_MTHD (dev, 0x005f, 0x018c, nv04_graph_mthd_bind_nv04_patt);
|
|
NVOBJ_MTHD (dev, 0x005f, 0x0190, nv04_graph_mthd_bind_rop);
|
|
NVOBJ_MTHD (dev, 0x005f, 0x0194, nv04_graph_mthd_bind_beta1);
|
|
NVOBJ_MTHD (dev, 0x005f, 0x0198, nv04_graph_mthd_bind_beta4);
|
|
NVOBJ_MTHD (dev, 0x005f, 0x019c, nv04_graph_mthd_bind_surf2d);
|
|
NVOBJ_MTHD (dev, 0x005f, 0x02fc, nv04_graph_mthd_set_operation);
|
|
|
|
/* nv04 iifc */
|
|
NVOBJ_CLASS(dev, 0x0060, GR);
|
|
NVOBJ_MTHD (dev, 0x0060, 0x0188, nv04_graph_mthd_bind_chroma);
|
|
NVOBJ_MTHD (dev, 0x0060, 0x018c, nv04_graph_mthd_bind_clip);
|
|
NVOBJ_MTHD (dev, 0x0060, 0x0190, nv04_graph_mthd_bind_nv04_patt);
|
|
NVOBJ_MTHD (dev, 0x0060, 0x0194, nv04_graph_mthd_bind_rop);
|
|
NVOBJ_MTHD (dev, 0x0060, 0x0198, nv04_graph_mthd_bind_beta1);
|
|
NVOBJ_MTHD (dev, 0x0060, 0x019c, nv04_graph_mthd_bind_beta4);
|
|
NVOBJ_MTHD (dev, 0x0060, 0x01a0, nv04_graph_mthd_bind_surf2d_swzsurf);
|
|
NVOBJ_MTHD (dev, 0x0060, 0x03e4, nv04_graph_mthd_set_operation);
|
|
|
|
/* nv05 iifc */
|
|
NVOBJ_CLASS(dev, 0x0064, GR);
|
|
|
|
/* nv01 ifc */
|
|
NVOBJ_CLASS(dev, 0x0021, GR);
|
|
NVOBJ_MTHD (dev, 0x0021, 0x0184, nv04_graph_mthd_bind_chroma);
|
|
NVOBJ_MTHD (dev, 0x0021, 0x0188, nv04_graph_mthd_bind_clip);
|
|
NVOBJ_MTHD (dev, 0x0021, 0x018c, nv04_graph_mthd_bind_nv01_patt);
|
|
NVOBJ_MTHD (dev, 0x0021, 0x0190, nv04_graph_mthd_bind_rop);
|
|
NVOBJ_MTHD (dev, 0x0021, 0x0194, nv04_graph_mthd_bind_beta1);
|
|
NVOBJ_MTHD (dev, 0x0021, 0x0198, nv04_graph_mthd_bind_surf_dst);
|
|
NVOBJ_MTHD (dev, 0x0021, 0x02fc, nv04_graph_mthd_set_operation);
|
|
|
|
/* nv04 ifc */
|
|
NVOBJ_CLASS(dev, 0x0061, GR);
|
|
NVOBJ_MTHD (dev, 0x0061, 0x0184, nv04_graph_mthd_bind_chroma);
|
|
NVOBJ_MTHD (dev, 0x0061, 0x0188, nv04_graph_mthd_bind_clip);
|
|
NVOBJ_MTHD (dev, 0x0061, 0x018c, nv04_graph_mthd_bind_nv04_patt);
|
|
NVOBJ_MTHD (dev, 0x0061, 0x0190, nv04_graph_mthd_bind_rop);
|
|
NVOBJ_MTHD (dev, 0x0061, 0x0194, nv04_graph_mthd_bind_beta1);
|
|
NVOBJ_MTHD (dev, 0x0061, 0x0198, nv04_graph_mthd_bind_beta4);
|
|
NVOBJ_MTHD (dev, 0x0061, 0x019c, nv04_graph_mthd_bind_surf2d);
|
|
NVOBJ_MTHD (dev, 0x0061, 0x02fc, nv04_graph_mthd_set_operation);
|
|
|
|
/* nv05 ifc */
|
|
NVOBJ_CLASS(dev, 0x0065, GR);
|
|
|
|
/* nv03 sifc */
|
|
NVOBJ_CLASS(dev, 0x0036, GR);
|
|
NVOBJ_MTHD (dev, 0x0036, 0x0184, nv04_graph_mthd_bind_chroma);
|
|
NVOBJ_MTHD (dev, 0x0036, 0x0188, nv04_graph_mthd_bind_nv01_patt);
|
|
NVOBJ_MTHD (dev, 0x0036, 0x018c, nv04_graph_mthd_bind_rop);
|
|
NVOBJ_MTHD (dev, 0x0036, 0x0190, nv04_graph_mthd_bind_beta1);
|
|
NVOBJ_MTHD (dev, 0x0036, 0x0194, nv04_graph_mthd_bind_surf_dst);
|
|
NVOBJ_MTHD (dev, 0x0036, 0x02fc, nv04_graph_mthd_set_operation);
|
|
|
|
/* nv04 sifc */
|
|
NVOBJ_CLASS(dev, 0x0076, GR);
|
|
NVOBJ_MTHD (dev, 0x0076, 0x0184, nv04_graph_mthd_bind_chroma);
|
|
NVOBJ_MTHD (dev, 0x0076, 0x0188, nv04_graph_mthd_bind_nv04_patt);
|
|
NVOBJ_MTHD (dev, 0x0076, 0x018c, nv04_graph_mthd_bind_rop);
|
|
NVOBJ_MTHD (dev, 0x0076, 0x0190, nv04_graph_mthd_bind_beta1);
|
|
NVOBJ_MTHD (dev, 0x0076, 0x0194, nv04_graph_mthd_bind_beta4);
|
|
NVOBJ_MTHD (dev, 0x0076, 0x0198, nv04_graph_mthd_bind_surf2d);
|
|
NVOBJ_MTHD (dev, 0x0076, 0x02fc, nv04_graph_mthd_set_operation);
|
|
|
|
/* nv05 sifc */
|
|
NVOBJ_CLASS(dev, 0x0066, GR);
|
|
|
|
/* nv03 sifm */
|
|
NVOBJ_CLASS(dev, 0x0037, GR);
|
|
NVOBJ_MTHD (dev, 0x0037, 0x0188, nv04_graph_mthd_bind_nv01_patt);
|
|
NVOBJ_MTHD (dev, 0x0037, 0x018c, nv04_graph_mthd_bind_rop);
|
|
NVOBJ_MTHD (dev, 0x0037, 0x0190, nv04_graph_mthd_bind_beta1);
|
|
NVOBJ_MTHD (dev, 0x0037, 0x0194, nv04_graph_mthd_bind_surf_dst);
|
|
NVOBJ_MTHD (dev, 0x0037, 0x0304, nv04_graph_mthd_set_operation);
|
|
|
|
/* nv04 sifm */
|
|
NVOBJ_CLASS(dev, 0x0077, GR);
|
|
NVOBJ_MTHD (dev, 0x0077, 0x0188, nv04_graph_mthd_bind_nv04_patt);
|
|
NVOBJ_MTHD (dev, 0x0077, 0x018c, nv04_graph_mthd_bind_rop);
|
|
NVOBJ_MTHD (dev, 0x0077, 0x0190, nv04_graph_mthd_bind_beta1);
|
|
NVOBJ_MTHD (dev, 0x0077, 0x0194, nv04_graph_mthd_bind_beta4);
|
|
NVOBJ_MTHD (dev, 0x0077, 0x0198, nv04_graph_mthd_bind_surf2d_swzsurf);
|
|
NVOBJ_MTHD (dev, 0x0077, 0x0304, nv04_graph_mthd_set_operation);
|
|
|
|
/* null */
|
|
NVOBJ_CLASS(dev, 0x0030, GR);
|
|
|
|
/* surf2d */
|
|
NVOBJ_CLASS(dev, 0x0042, GR);
|
|
|
|
/* rop */
|
|
NVOBJ_CLASS(dev, 0x0043, GR);
|
|
|
|
/* beta1 */
|
|
NVOBJ_CLASS(dev, 0x0012, GR);
|
|
|
|
/* beta4 */
|
|
NVOBJ_CLASS(dev, 0x0072, GR);
|
|
|
|
/* cliprect */
|
|
NVOBJ_CLASS(dev, 0x0019, GR);
|
|
|
|
/* nv01 pattern */
|
|
NVOBJ_CLASS(dev, 0x0018, GR);
|
|
|
|
/* nv04 pattern */
|
|
NVOBJ_CLASS(dev, 0x0044, GR);
|
|
|
|
/* swzsurf */
|
|
NVOBJ_CLASS(dev, 0x0052, GR);
|
|
|
|
/* surf3d */
|
|
NVOBJ_CLASS(dev, 0x0053, GR);
|
|
NVOBJ_MTHD (dev, 0x0053, 0x02f8, nv04_graph_mthd_surf3d_clip_h);
|
|
NVOBJ_MTHD (dev, 0x0053, 0x02fc, nv04_graph_mthd_surf3d_clip_v);
|
|
|
|
/* nv03 tex_tri */
|
|
NVOBJ_CLASS(dev, 0x0048, GR);
|
|
NVOBJ_MTHD (dev, 0x0048, 0x0188, nv04_graph_mthd_bind_clip);
|
|
NVOBJ_MTHD (dev, 0x0048, 0x018c, nv04_graph_mthd_bind_surf_color);
|
|
NVOBJ_MTHD (dev, 0x0048, 0x0190, nv04_graph_mthd_bind_surf_zeta);
|
|
|
|
/* tex_tri */
|
|
NVOBJ_CLASS(dev, 0x0054, GR);
|
|
|
|
/* multitex_tri */
|
|
NVOBJ_CLASS(dev, 0x0055, GR);
|
|
|
|
/* nv01 chroma */
|
|
NVOBJ_CLASS(dev, 0x0017, GR);
|
|
|
|
/* nv04 chroma */
|
|
NVOBJ_CLASS(dev, 0x0057, GR);
|
|
|
|
/* surf_dst */
|
|
NVOBJ_CLASS(dev, 0x0058, GR);
|
|
|
|
/* surf_src */
|
|
NVOBJ_CLASS(dev, 0x0059, GR);
|
|
|
|
/* surf_color */
|
|
NVOBJ_CLASS(dev, 0x005a, GR);
|
|
|
|
/* surf_zeta */
|
|
NVOBJ_CLASS(dev, 0x005b, GR);
|
|
|
|
/* nv01 line */
|
|
NVOBJ_CLASS(dev, 0x001c, GR);
|
|
NVOBJ_MTHD (dev, 0x001c, 0x0184, nv04_graph_mthd_bind_clip);
|
|
NVOBJ_MTHD (dev, 0x001c, 0x0188, nv04_graph_mthd_bind_nv01_patt);
|
|
NVOBJ_MTHD (dev, 0x001c, 0x018c, nv04_graph_mthd_bind_rop);
|
|
NVOBJ_MTHD (dev, 0x001c, 0x0190, nv04_graph_mthd_bind_beta1);
|
|
NVOBJ_MTHD (dev, 0x001c, 0x0194, nv04_graph_mthd_bind_surf_dst);
|
|
NVOBJ_MTHD (dev, 0x001c, 0x02fc, nv04_graph_mthd_set_operation);
|
|
|
|
/* nv04 line */
|
|
NVOBJ_CLASS(dev, 0x005c, GR);
|
|
NVOBJ_MTHD (dev, 0x005c, 0x0184, nv04_graph_mthd_bind_clip);
|
|
NVOBJ_MTHD (dev, 0x005c, 0x0188, nv04_graph_mthd_bind_nv04_patt);
|
|
NVOBJ_MTHD (dev, 0x005c, 0x018c, nv04_graph_mthd_bind_rop);
|
|
NVOBJ_MTHD (dev, 0x005c, 0x0190, nv04_graph_mthd_bind_beta1);
|
|
NVOBJ_MTHD (dev, 0x005c, 0x0194, nv04_graph_mthd_bind_beta4);
|
|
NVOBJ_MTHD (dev, 0x005c, 0x0198, nv04_graph_mthd_bind_surf2d);
|
|
NVOBJ_MTHD (dev, 0x005c, 0x02fc, nv04_graph_mthd_set_operation);
|
|
|
|
/* nv01 tri */
|
|
NVOBJ_CLASS(dev, 0x001d, GR);
|
|
NVOBJ_MTHD (dev, 0x001d, 0x0184, nv04_graph_mthd_bind_clip);
|
|
NVOBJ_MTHD (dev, 0x001d, 0x0188, nv04_graph_mthd_bind_nv01_patt);
|
|
NVOBJ_MTHD (dev, 0x001d, 0x018c, nv04_graph_mthd_bind_rop);
|
|
NVOBJ_MTHD (dev, 0x001d, 0x0190, nv04_graph_mthd_bind_beta1);
|
|
NVOBJ_MTHD (dev, 0x001d, 0x0194, nv04_graph_mthd_bind_surf_dst);
|
|
NVOBJ_MTHD (dev, 0x001d, 0x02fc, nv04_graph_mthd_set_operation);
|
|
|
|
/* nv04 tri */
|
|
NVOBJ_CLASS(dev, 0x005d, GR);
|
|
NVOBJ_MTHD (dev, 0x005d, 0x0184, nv04_graph_mthd_bind_clip);
|
|
NVOBJ_MTHD (dev, 0x005d, 0x0188, nv04_graph_mthd_bind_nv04_patt);
|
|
NVOBJ_MTHD (dev, 0x005d, 0x018c, nv04_graph_mthd_bind_rop);
|
|
NVOBJ_MTHD (dev, 0x005d, 0x0190, nv04_graph_mthd_bind_beta1);
|
|
NVOBJ_MTHD (dev, 0x005d, 0x0194, nv04_graph_mthd_bind_beta4);
|
|
NVOBJ_MTHD (dev, 0x005d, 0x0198, nv04_graph_mthd_bind_surf2d);
|
|
NVOBJ_MTHD (dev, 0x005d, 0x02fc, nv04_graph_mthd_set_operation);
|
|
|
|
/* nv01 rect */
|
|
NVOBJ_CLASS(dev, 0x001e, GR);
|
|
NVOBJ_MTHD (dev, 0x001e, 0x0184, nv04_graph_mthd_bind_clip);
|
|
NVOBJ_MTHD (dev, 0x001e, 0x0188, nv04_graph_mthd_bind_nv01_patt);
|
|
NVOBJ_MTHD (dev, 0x001e, 0x018c, nv04_graph_mthd_bind_rop);
|
|
NVOBJ_MTHD (dev, 0x001e, 0x0190, nv04_graph_mthd_bind_beta1);
|
|
NVOBJ_MTHD (dev, 0x001e, 0x0194, nv04_graph_mthd_bind_surf_dst);
|
|
NVOBJ_MTHD (dev, 0x001e, 0x02fc, nv04_graph_mthd_set_operation);
|
|
|
|
/* nv04 rect */
|
|
NVOBJ_CLASS(dev, 0x005e, GR);
|
|
NVOBJ_MTHD (dev, 0x005e, 0x0184, nv04_graph_mthd_bind_clip);
|
|
NVOBJ_MTHD (dev, 0x005e, 0x0188, nv04_graph_mthd_bind_nv04_patt);
|
|
NVOBJ_MTHD (dev, 0x005e, 0x018c, nv04_graph_mthd_bind_rop);
|
|
NVOBJ_MTHD (dev, 0x005e, 0x0190, nv04_graph_mthd_bind_beta1);
|
|
NVOBJ_MTHD (dev, 0x005e, 0x0194, nv04_graph_mthd_bind_beta4);
|
|
NVOBJ_MTHD (dev, 0x005e, 0x0198, nv04_graph_mthd_bind_surf2d);
|
|
NVOBJ_MTHD (dev, 0x005e, 0x02fc, nv04_graph_mthd_set_operation);
|
|
|
|
/* nvsw */
|
|
NVOBJ_CLASS(dev, 0x506e, SW);
|
|
NVOBJ_MTHD (dev, 0x506e, 0x0150, nv04_graph_mthd_set_ref);
|
|
NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
|
|
|
|
dev_priv->engine.graph.registered = true;
|
|
return 0;
|
|
};
|
|
|
|
static struct nouveau_bitfield nv04_graph_intr[] = {
|
|
{ NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
|
|
{}
|
|
};
|
|
|
|
static struct nouveau_bitfield nv04_graph_nstatus[] =
|
|
{
|
|
{ NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
|
|
{ NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
|
|
{ NV04_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
|
|
{ NV04_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" },
|
|
{}
|
|
};
|
|
|
|
struct nouveau_bitfield nv04_graph_nsource[] =
|
|
{
|
|
{ NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" },
|
|
{ NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" },
|
|
{ NV03_PGRAPH_NSOURCE_PROTECTION_ERROR, "PROTECTION_ERROR" },
|
|
{ NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION, "RANGE_EXCEPTION" },
|
|
{ NV03_PGRAPH_NSOURCE_LIMIT_COLOR, "LIMIT_COLOR" },
|
|
{ NV03_PGRAPH_NSOURCE_LIMIT_ZETA, "LIMIT_ZETA" },
|
|
{ NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD, "ILLEGAL_MTHD" },
|
|
{ NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION, "DMA_R_PROTECTION" },
|
|
{ NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION, "DMA_W_PROTECTION" },
|
|
{ NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION, "FORMAT_EXCEPTION" },
|
|
{ NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION, "PATCH_EXCEPTION" },
|
|
{ NV03_PGRAPH_NSOURCE_STATE_INVALID, "STATE_INVALID" },
|
|
{ NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY, "DOUBLE_NOTIFY" },
|
|
{ NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE, "NOTIFY_IN_USE" },
|
|
{ NV03_PGRAPH_NSOURCE_METHOD_CNT, "METHOD_CNT" },
|
|
{ NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION, "BFR_NOTIFICATION" },
|
|
{ NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
|
|
{ NV03_PGRAPH_NSOURCE_DMA_WIDTH_A, "DMA_WIDTH_A" },
|
|
{ NV03_PGRAPH_NSOURCE_DMA_WIDTH_B, "DMA_WIDTH_B" },
|
|
{}
|
|
};
|
|
|
|
static void
|
|
nv04_graph_isr(struct drm_device *dev)
|
|
{
|
|
u32 stat;
|
|
|
|
while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
|
|
u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
|
|
u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
|
|
u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
|
|
u32 chid = (addr & 0x0f000000) >> 24;
|
|
u32 subc = (addr & 0x0000e000) >> 13;
|
|
u32 mthd = (addr & 0x00001ffc);
|
|
u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
|
|
u32 class = nv_rd32(dev, 0x400180 + subc * 4) & 0xff;
|
|
u32 show = stat;
|
|
|
|
if (stat & NV_PGRAPH_INTR_NOTIFY) {
|
|
if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
|
|
if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
|
|
show &= ~NV_PGRAPH_INTR_NOTIFY;
|
|
}
|
|
}
|
|
|
|
if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
|
|
nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
|
|
stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
|
|
show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
|
|
nv04_graph_context_switch(dev);
|
|
}
|
|
|
|
nv_wr32(dev, NV03_PGRAPH_INTR, stat);
|
|
nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
|
|
|
|
if (show && nouveau_ratelimit()) {
|
|
NV_INFO(dev, "PGRAPH -");
|
|
nouveau_bitfield_print(nv04_graph_intr, show);
|
|
printk(" nsource:");
|
|
nouveau_bitfield_print(nv04_graph_nsource, nsource);
|
|
printk(" nstatus:");
|
|
nouveau_bitfield_print(nv04_graph_nstatus, nstatus);
|
|
printk("\n");
|
|
NV_INFO(dev, "PGRAPH - ch %d/%d class 0x%04x "
|
|
"mthd 0x%04x data 0x%08x\n",
|
|
chid, subc, class, mthd, data);
|
|
}
|
|
}
|
|
}
|