AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-11-30 09:56:40 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity
2ea6263068
linux_dsm_epyc7002/arch/riscv/kernel
History
Linus Torvalds 6a4d4b3253 RISC-V Updates for the 4.18 Merge Window 
This tag contains some small RISC-V updates I'd like to target for 4.18.
 They are all fairly small this time.  Here's a short summary, there's
 more info in the commits/merges.
 
 * A fix to __clear_user to respect the passed arguments.
 * Enough support for the perf subsystem to work with RISC-V's ISA
   defined performance counters.
 * Support for sparse and cleanups suggested by it.
 * Support for R_RISCV_32 (a relocation, not the 32-bit ISA).
 * Some MAINTAINERS cleanups.
 * The addition of CONFIG_HVC_RISCV_SBI to our defconfig, as it's always
   present.
 
 I've given these a simple build+boot test.
 -----BEGIN PGP SIGNATURE-----
 
 iQJHBAABCAAxFiEEAM520YNJYN/OiG3470yhUCzLq0EFAlsezeQTHHBhbG1lckBk
 YWJiZWx0LmNvbQAKCRDvTKFQLMurQSjWD/999J5HKkHQfHJi4/RQh0SEFNnRv32U
 1O7zwqA5PkeoxWqq1y+dKcPGwZTZncwWp8yn8xipVYTYmYgGNZj9CYdEYkO119y5
 OVcyUZdHlSdXgKkpVDJ0+MrZ60LY6tS66b6oJqQKmB/N4rYvu5L6ctRtyHRQe4nb
 rXNVbnaouiwrFJs9iZaCyaaGAGXKg81C5xCvvr8P0CYzVD4Jx+AmD6c7GohGWJS3
 PLttEsmPaiaV9pzWK18yeFLaIgAqNEo2/s7/QsR1sHo4dUEJyFu9nMHvmjlJucCu
 imrkRwlhsCKxa4ob9D6UPh0qBXDmbSQA1U6M9RKY1jdt7Gul5eMuZIz2r/45752D
 z3YCITgTih2dzWO0zw4GCicCcJoD39IVTrsRCIqxF7jmAfBV8s/U+irMjEMkYhz6
 wKVM9L3/6Z4bPAEztqKMjSw1/nNSavyn6wWACYIj5SDtFqNkvxwSahg1nGTuuoNx
 JqRa0r+lxsbunSwpEVtRROLYE3ZYa/KPrKhKEr+7vkiPlNNv82TZ5T/wkObhVfKp
 S6tZ0/Wb0tchm//LurfLAOV4aZxDlOLfukZ3eSdgBqSfILA3T98zS9FpuCmjiUfG
 6S5GdNvjc3jLLZvPwtofIZmKUSpRSj545J1RRkEcgoEFjXdzxOWFLETsIOIt4nFf
 7Nwjw/Th1hzuyQ==
 =D+sb
 -----END PGP SIGNATURE-----

Merge tag 'riscv-for-linus-4.18-merge_window' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux

Pull RISC-V updates from Palmer Dabbelt:
 "This contains some small RISC-V updates I'd like to target for 4.18.

  They are all fairly small this time. Here's a short summary, there's
  more info in the commits/merges:

   - a fix to __clear_user to respect the passed arguments.

   - enough support for the perf subsystem to work with RISC-V's ISA
     defined performance counters.

   - support for sparse and cleanups suggested by it.

   - support for R_RISCV_32 (a relocation, not the 32-bit ISA).

   - some MAINTAINERS cleanups.

   - the addition of CONFIG_HVC_RISCV_SBI to our defconfig, as it's
     always present.

  I've given these a simple build+boot test"

* tag 'riscv-for-linus-4.18-merge_window' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux:
  RISC-V: Add CONFIG_HVC_RISCV_SBI=y to defconfig
  RISC-V: Handle R_RISCV_32 in modules
  riscv/ftrace: Export _mcount when DYNAMIC_FTRACE isn't set
  riscv: add riscv-specific predefines to CHECKFLAGS
  riscv: split the declaration of __copy_user
  riscv: no __user for probe_kernel_address()
  riscv: use NULL instead of a plain 0
  perf: riscv: Add Document for Future Porting Guide
  perf: riscv: preliminary RISC-V support
  MAINTAINERS: Update Albert's email, he's back at Berkeley
  MAINTAINERS: Add myself as a maintainer for SiFive's drivers
  riscv: Fix the bug in memory access fixup code
2018-06-16 06:42:43 +09:00
..
vdso RISC-V: build vdso-dummy.o with -no-pie 2018-04-24 10:54:46 -07:00
.gitignore RISC-V: Build Infrastructure 2017-09-26 15:26:49 -07:00
asm-offsets.c RISC-V: Task implementation 2017-09-26 15:26:46 -07:00
cacheinfo.c drivers: base: cacheinfo: setup DT cache properties early 2018-05-17 17:27:49 +01:00
cpu.c RISC-V: Init and Halt Code 2017-09-26 15:26:44 -07:00
cpufeature.c RISC-V: User-facing API 2017-09-26 15:26:48 -07:00
entry.S RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler 2018-03-14 21:46:29 +01:00
ftrace.c riscv/ftrace: Add HAVE_FUNCTION_GRAPH_RET_ADDR_PTR support 2018-04-02 19:59:13 -07:00
head.S Rename sbi_save to parse_dtb to improve code readability 2018-02-20 10:56:26 -08:00
irq.c RISC-V: Move to the new GENERIC_IRQ_MULTI_HANDLER handler 2018-03-14 21:46:29 +01:00
Makefile perf: riscv: preliminary RISC-V support 2018-06-04 14:02:01 -07:00
mcount-dyn.S riscv/ftrace: Add DYNAMIC_FTRACE_WITH_REGS support 2018-04-02 19:59:13 -07:00
mcount.S riscv/ftrace: Export _mcount when DYNAMIC_FTRACE isn't set 2018-06-11 09:04:03 -07:00
module-sections.c RISC-V: Add section of GOT.PLT for kernel module 2018-04-02 20:00:54 -07:00
module.c RISC-V: Handle R_RISCV_32 in modules 2018-06-11 09:04:34 -07:00
module.lds RISC-V: Add section of GOT.PLT for kernel module 2018-04-02 20:00:54 -07:00
perf_event.c perf: riscv: preliminary RISC-V support 2018-06-04 14:02:01 -07:00
process.c Merge branch 'work.whack-a-mole' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs 2018-01-31 19:18:12 -08:00
ptrace.c RISC-V: User-facing API 2017-09-26 15:26:48 -07:00
reset.c RISC-V: Init and Halt Code 2017-09-26 15:26:44 -07:00
riscv_ksyms.c riscv: split the declaration of __copy_user 2018-06-09 12:34:31 -07:00
setup.c riscv: add swiotlb support 2018-05-19 08:46:26 +02:00
signal.c RISC-V: User-facing API 2017-09-26 15:26:48 -07:00
smp.c RISC-V: Fixes for clean allmodconfig build 2017-12-01 13:31:31 -08:00
smpboot.c RISC-V: Init and Halt Code 2017-09-26 15:26:44 -07:00
stacktrace.c riscv/ftrace: Add HAVE_FUNCTION_GRAPH_RET_ADDR_PTR support 2018-04-02 19:59:13 -07:00
sys_riscv.c mm: add ksys_mmap_pgoff() helper; remove in-kernel calls to sys_mmap_pgoff() 2018-04-02 20:16:11 +02:00
syscall_table.c RISC-V: Make __NR_riscv_flush_icache visible to userspace 2018-01-07 15:14:37 -08:00
time.c RISC-V: Init and Halt Code 2017-09-26 15:26:44 -07:00
traps.c RISC-V Updates for the 4.18 Merge Window 2018-06-16 06:42:43 +09:00
vdso.c riscv: remove redundant unlikely() 2018-01-30 19:12:06 -08:00
vmlinux.lds.S RISC-V: Build Infrastructure 2017-09-26 15:26:49 -07:00