mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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be01da72b1
Rather than have each driver set the driver owner field, do it once in the core code. This will also help with later changes, when the device structure will move. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
419 lines
12 KiB
C
419 lines
12 KiB
C
/*
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* Broadcom BCM7xxx internal transceivers support.
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*
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* Copyright (C) 2014, Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/delay.h>
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#include "bcm-phy-lib.h"
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#include <linux/bitops.h>
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#include <linux/brcmphy.h>
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#include <linux/mdio.h>
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/* Broadcom BCM7xxx internal PHY registers */
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/* 40nm only register definitions */
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#define MII_BCM7XXX_100TX_AUX_CTL 0x10
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#define MII_BCM7XXX_100TX_FALSE_CAR 0x13
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#define MII_BCM7XXX_100TX_DISC 0x14
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#define MII_BCM7XXX_AUX_MODE 0x1d
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#define MII_BCM7XX_64CLK_MDIO BIT(12)
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#define MII_BCM7XXX_TEST 0x1f
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#define MII_BCM7XXX_SHD_MODE_2 BIT(2)
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/* 28nm only register definitions */
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#define MISC_ADDR(base, channel) base, channel
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#define DSP_TAP10 MISC_ADDR(0x0a, 0)
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#define PLL_PLLCTRL_1 MISC_ADDR(0x32, 1)
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#define PLL_PLLCTRL_2 MISC_ADDR(0x32, 2)
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#define PLL_PLLCTRL_4 MISC_ADDR(0x33, 0)
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#define AFE_RXCONFIG_0 MISC_ADDR(0x38, 0)
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#define AFE_RXCONFIG_1 MISC_ADDR(0x38, 1)
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#define AFE_RXCONFIG_2 MISC_ADDR(0x38, 2)
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#define AFE_RX_LP_COUNTER MISC_ADDR(0x38, 3)
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#define AFE_TX_CONFIG MISC_ADDR(0x39, 0)
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#define AFE_VDCA_ICTRL_0 MISC_ADDR(0x39, 1)
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#define AFE_VDAC_OTHERS_0 MISC_ADDR(0x39, 3)
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#define AFE_HPF_TRIM_OTHERS MISC_ADDR(0x3a, 0)
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static void r_rc_cal_reset(struct phy_device *phydev)
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{
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/* Reset R_CAL/RC_CAL Engine */
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bcm_phy_write_exp(phydev, 0x00b0, 0x0010);
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/* Disable Reset R_AL/RC_CAL Engine */
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bcm_phy_write_exp(phydev, 0x00b0, 0x0000);
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}
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static int bcm7xxx_28nm_b0_afe_config_init(struct phy_device *phydev)
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{
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/* Increase VCO range to prevent unlocking problem of PLL at low
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* temp
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*/
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bcm_phy_write_misc(phydev, PLL_PLLCTRL_1, 0x0048);
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/* Change Ki to 011 */
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bcm_phy_write_misc(phydev, PLL_PLLCTRL_2, 0x021b);
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/* Disable loading of TVCO buffer to bandgap, set bandgap trim
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* to 111
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*/
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bcm_phy_write_misc(phydev, PLL_PLLCTRL_4, 0x0e20);
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/* Adjust bias current trim by -3 */
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bcm_phy_write_misc(phydev, DSP_TAP10, 0x690b);
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/* Switch to CORE_BASE1E */
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phy_write(phydev, MII_BRCM_CORE_BASE1E, 0xd);
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r_rc_cal_reset(phydev);
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/* write AFE_RXCONFIG_0 */
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bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb19);
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/* write AFE_RXCONFIG_1 */
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bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9a3f);
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/* write AFE_RX_LP_COUNTER */
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bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
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/* write AFE_HPF_TRIM_OTHERS */
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bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x000b);
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/* write AFTE_TX_CONFIG */
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bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x0800);
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return 0;
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}
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static int bcm7xxx_28nm_d0_afe_config_init(struct phy_device *phydev)
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{
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/* AFE_RXCONFIG_0 */
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bcm_phy_write_misc(phydev, AFE_RXCONFIG_0, 0xeb15);
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/* AFE_RXCONFIG_1 */
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bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
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/* AFE_RXCONFIG_2, set rCal offset for HT=0 code and LT=-2 code */
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bcm_phy_write_misc(phydev, AFE_RXCONFIG_2, 0x2003);
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/* AFE_RX_LP_COUNTER, set RX bandwidth to maximum */
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bcm_phy_write_misc(phydev, AFE_RX_LP_COUNTER, 0x7fc0);
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/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
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bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
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/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
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bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
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/* AFE_VDAC_OTHERS_0, set 1000BT Cidac=010 for all ports */
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bcm_phy_write_misc(phydev, AFE_VDAC_OTHERS_0, 0xa020);
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/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
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* offset for HT=0 code
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*/
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bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
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/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
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phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
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/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
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bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
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/* Reset R_CAL/RC_CAL engine */
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r_rc_cal_reset(phydev);
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return 0;
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}
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static int bcm7xxx_28nm_e0_plus_afe_config_init(struct phy_device *phydev)
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{
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/* AFE_RXCONFIG_1, provide more margin for INL/DNL measurement */
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bcm_phy_write_misc(phydev, AFE_RXCONFIG_1, 0x9b2f);
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/* AFE_TX_CONFIG, set 100BT Cfeed=011 to improve rise/fall time */
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bcm_phy_write_misc(phydev, AFE_TX_CONFIG, 0x431);
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/* AFE_VDCA_ICTRL_0, set Iq=1101 instead of 0111 for AB symmetry */
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bcm_phy_write_misc(phydev, AFE_VDCA_ICTRL_0, 0xa7da);
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/* AFE_HPF_TRIM_OTHERS, set 100Tx/10BT to -4.5% swing and set rCal
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* offset for HT=0 code
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*/
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bcm_phy_write_misc(phydev, AFE_HPF_TRIM_OTHERS, 0x00e3);
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/* CORE_BASE1E, force trim to overwrite and set I_ext trim to 0000 */
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phy_write(phydev, MII_BRCM_CORE_BASE1E, 0x0010);
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/* DSP_TAP10, adjust bias current trim (+0% swing, +0 tick) */
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bcm_phy_write_misc(phydev, DSP_TAP10, 0x011b);
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/* Reset R_CAL/RC_CAL engine */
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r_rc_cal_reset(phydev);
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return 0;
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}
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static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
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{
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u8 rev = PHY_BRCM_7XXX_REV(phydev->dev_flags);
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u8 patch = PHY_BRCM_7XXX_PATCH(phydev->dev_flags);
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int ret = 0;
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pr_info_once("%s: %s PHY revision: 0x%02x, patch: %d\n",
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phydev_name(phydev), phydev->drv->name, rev, patch);
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/* Dummy read to a register to workaround an issue upon reset where the
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* internal inverter may not allow the first MDIO transaction to pass
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* the MDIO management controller and make us return 0xffff for such
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* reads.
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*/
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phy_read(phydev, MII_BMSR);
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switch (rev) {
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case 0xb0:
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ret = bcm7xxx_28nm_b0_afe_config_init(phydev);
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break;
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case 0xd0:
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ret = bcm7xxx_28nm_d0_afe_config_init(phydev);
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break;
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case 0xe0:
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case 0xf0:
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/* Rev G0 introduces a roll over */
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case 0x10:
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ret = bcm7xxx_28nm_e0_plus_afe_config_init(phydev);
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break;
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default:
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break;
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}
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if (ret)
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return ret;
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ret = bcm_phy_enable_eee(phydev);
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if (ret)
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return ret;
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return bcm_phy_enable_apd(phydev, true);
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}
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static int bcm7xxx_28nm_resume(struct phy_device *phydev)
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{
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int ret;
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/* Re-apply workarounds coming out suspend/resume */
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ret = bcm7xxx_28nm_config_init(phydev);
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if (ret)
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return ret;
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/* 28nm Gigabit PHYs come out of reset without any half-duplex
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* or "hub" compliant advertised mode, fix that. This does not
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* cause any problems with the PHY library since genphy_config_aneg()
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* gracefully handles auto-negotiated and forced modes.
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*/
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return genphy_config_aneg(phydev);
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}
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static int phy_set_clr_bits(struct phy_device *dev, int location,
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int set_mask, int clr_mask)
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{
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int v, ret;
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v = phy_read(dev, location);
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if (v < 0)
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return v;
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v &= ~clr_mask;
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v |= set_mask;
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ret = phy_write(dev, location, v);
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if (ret < 0)
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return ret;
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return v;
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}
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static int bcm7xxx_config_init(struct phy_device *phydev)
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{
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int ret;
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/* Enable 64 clock MDIO */
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phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XX_64CLK_MDIO);
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phy_read(phydev, MII_BCM7XXX_AUX_MODE);
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/* Workaround only required for 100Mbits/sec capable PHYs */
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if (phydev->supported & PHY_GBIT_FEATURES)
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return 0;
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/* set shadow mode 2 */
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ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
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MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2);
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if (ret < 0)
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return ret;
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/* set iddq_clkbias */
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phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
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udelay(10);
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/* reset iddq_clkbias */
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phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);
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phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);
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/* reset shadow mode 2 */
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ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, MII_BCM7XXX_SHD_MODE_2, 0);
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if (ret < 0)
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return ret;
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return 0;
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}
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/* Workaround for putting the PHY in IDDQ mode, required
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* for all BCM7XXX 40nm and 65nm PHYs
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*/
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static int bcm7xxx_suspend(struct phy_device *phydev)
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{
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int ret;
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const struct bcm7xxx_regs {
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int reg;
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u16 value;
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} bcm7xxx_suspend_cfg[] = {
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{ MII_BCM7XXX_TEST, 0x008b },
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{ MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 },
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{ MII_BCM7XXX_100TX_DISC, 0x7000 },
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{ MII_BCM7XXX_TEST, 0x000f },
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{ MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 },
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{ MII_BCM7XXX_TEST, 0x000b },
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};
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) {
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ret = phy_write(phydev,
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bcm7xxx_suspend_cfg[i].reg,
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bcm7xxx_suspend_cfg[i].value);
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if (ret)
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return ret;
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}
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return 0;
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}
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static int bcm7xxx_dummy_config_init(struct phy_device *phydev)
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{
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return 0;
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}
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#define BCM7XXX_28NM_GPHY(_oui, _name) \
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{ \
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.phy_id = (_oui), \
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.phy_id_mask = 0xfffffff0, \
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.name = _name, \
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.features = PHY_GBIT_FEATURES | \
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SUPPORTED_Pause | SUPPORTED_Asym_Pause, \
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.flags = PHY_IS_INTERNAL, \
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.config_init = bcm7xxx_28nm_config_init, \
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.config_aneg = genphy_config_aneg, \
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.read_status = genphy_read_status, \
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.resume = bcm7xxx_28nm_resume, \
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}
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static struct phy_driver bcm7xxx_driver[] = {
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BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
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BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
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BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
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BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
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BCM7XXX_28NM_GPHY(PHY_ID_BCM7439_2, "Broadcom BCM7439 (2)"),
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BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
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{
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.phy_id = PHY_ID_BCM7425,
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.phy_id_mask = 0xfffffff0,
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.name = "Broadcom BCM7425",
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.features = PHY_GBIT_FEATURES |
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SUPPORTED_Pause | SUPPORTED_Asym_Pause,
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.flags = PHY_IS_INTERNAL,
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.config_init = bcm7xxx_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.suspend = bcm7xxx_suspend,
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.resume = bcm7xxx_config_init,
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}, {
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.phy_id = PHY_ID_BCM7429,
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.phy_id_mask = 0xfffffff0,
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.name = "Broadcom BCM7429",
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.features = PHY_GBIT_FEATURES |
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SUPPORTED_Pause | SUPPORTED_Asym_Pause,
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.flags = PHY_IS_INTERNAL,
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.config_init = bcm7xxx_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.suspend = bcm7xxx_suspend,
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.resume = bcm7xxx_config_init,
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}, {
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.phy_id = PHY_ID_BCM7435,
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.phy_id_mask = 0xfffffff0,
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.name = "Broadcom BCM7435",
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.features = PHY_GBIT_FEATURES |
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SUPPORTED_Pause | SUPPORTED_Asym_Pause,
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.flags = PHY_IS_INTERNAL,
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.config_init = bcm7xxx_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.suspend = bcm7xxx_suspend,
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.resume = bcm7xxx_config_init,
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}, {
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.phy_id = PHY_BCM_OUI_4,
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.phy_id_mask = 0xffff0000,
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.name = "Broadcom BCM7XXX 40nm",
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.features = PHY_GBIT_FEATURES |
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SUPPORTED_Pause | SUPPORTED_Asym_Pause,
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.flags = PHY_IS_INTERNAL,
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.config_init = bcm7xxx_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.suspend = bcm7xxx_suspend,
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.resume = bcm7xxx_config_init,
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}, {
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.phy_id = PHY_BCM_OUI_5,
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.phy_id_mask = 0xffffff00,
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.name = "Broadcom BCM7XXX 65nm",
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.features = PHY_BASIC_FEATURES |
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SUPPORTED_Pause | SUPPORTED_Asym_Pause,
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.flags = PHY_IS_INTERNAL,
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.config_init = bcm7xxx_dummy_config_init,
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.config_aneg = genphy_config_aneg,
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.read_status = genphy_read_status,
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.suspend = bcm7xxx_suspend,
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.resume = bcm7xxx_config_init,
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} };
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static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
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{ PHY_ID_BCM7250, 0xfffffff0, },
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{ PHY_ID_BCM7364, 0xfffffff0, },
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{ PHY_ID_BCM7366, 0xfffffff0, },
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{ PHY_ID_BCM7425, 0xfffffff0, },
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{ PHY_ID_BCM7429, 0xfffffff0, },
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{ PHY_ID_BCM7439, 0xfffffff0, },
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{ PHY_ID_BCM7435, 0xfffffff0, },
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{ PHY_ID_BCM7445, 0xfffffff0, },
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{ PHY_BCM_OUI_4, 0xffff0000 },
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{ PHY_BCM_OUI_5, 0xffffff00 },
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{ }
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};
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module_phy_driver(bcm7xxx_driver);
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MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);
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MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Broadcom Corporation");
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