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f43d1b388f
Add ROHM BD71837 / BD71847 specific device tree bindings for controlling the PMIC shutdown/reset states and voltages for different HW states. The PMIC was designed to be used with NXP i.MX8 SoC and it supports SNVS low power state which seems to be typical for NXP i.MX SoCs. However, when SNVS is used we must not allow SW to control enabling/disabling those regulators which are crucial for system to boot as there is a HW limitation which causes SW controlled regulators to be kept shut down after SNVS reset. Allow setting the SNVS to be used as reset target state and allow marking those regulators which are critical for boot. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Tested-by: Angus Ainslie <angus@akkea.ca> Reviewed-by: Angus Ainslie <angus@akkea.ca> Signed-off-by: Mark Brown <broonie@kernel.org>
81 lines
2.8 KiB
Plaintext
81 lines
2.8 KiB
Plaintext
* ROHM BD71837 and BD71847 Power Management Integrated Circuit bindings
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BD71837MWV and BD71847MWV are programmable Power Management ICs for powering
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single-core, dual-core, and quad-core SoCs such as NXP-i.MX 8M. They are
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optimized for low BOM cost and compact solution footprint. BD71837MWV
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integrates 8 Buck regulators and 7 LDOs. BD71847MWV contains 6 Buck regulators
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and 6 LDOs.
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Datasheet for BD71837 is available at:
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https://www.rohm.com/datasheet/BD71837MWV/bd71837mwv-e
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Required properties:
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- compatible : Should be "rohm,bd71837" for bd71837
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"rohm,bd71847" for bd71847.
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- reg : I2C slave address.
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- interrupt-parent : Phandle to the parent interrupt controller.
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- interrupts : The interrupt line the device is connected to.
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- clocks : The parent clock connected to PMIC. If this is missing
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32768 KHz clock is assumed.
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- #clock-cells : Should be 0.
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- regulators: : List of child nodes that specify the regulators.
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Please see ../regulator/rohm,bd71837-regulator.txt
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Optional properties:
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- clock-output-names : Should contain name for output clock.
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- rohm,reset-snvs-powered : Transfer BD718x7 to SNVS state at reset.
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The BD718x7 supports two different HW states as reset target states. States
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are called as SNVS and READY. At READY state all the PMIC power outputs go
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down and OTP is reload. At the SNVS state all other logic and external
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devices apart from the SNVS power domain are shut off. Please refer to NXP
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i.MX8 documentation for further information regarding SNVS state. When a
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reset is done via SNVS state the PMIC OTP data is not reload. This causes
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power outputs that have been under SW control to stay down when reset has
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switched power state to SNVS. If reset is done via READY state the power
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outputs will be returned to HW control by OTP loading. Thus the reset
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target state is set to READY by default. If SNVS state is used the boot
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crucial regulators must have the regulator-always-on and regulator-boot-on
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properties set in regulator node.
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Example:
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/* external oscillator node */
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osc: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <1>;
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clock-frequency = <32768>;
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clock-output-names = "osc";
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};
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pmic: pmic@4b {
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compatible = "rohm,bd71837";
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reg = <0x4b>;
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interrupt-parent = <&gpio1>;
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interrupts = <29 GPIO_ACTIVE_LOW>;
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interrupt-names = "irq";
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#clock-cells = <0>;
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clocks = <&osc 0>;
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clock-output-names = "bd71837-32k-out";
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rohm,reset-snvs-powered;
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regulators {
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buck1: BUCK1 {
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regulator-name = "buck1";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <1250>;
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};
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// [...]
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};
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};
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/* Clock consumer node */
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rtc@0 {
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compatible = "company,my-rtc";
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clock-names = "my-clock";
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clocks = <&pmic>;
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};
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