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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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71f5c63c07
This patch adds support for MIPI DPHYs found in Exynos5420-compatible (5420, 5422 and 5800) and Exynos5433 SoCs. Those SoCs differs from earlier by different offset of MIPI DPHY registers in PMU controllers (Exynos 5420-compatible case) or by moving MIPI DPHY reset registers to separate system register controllers (Exynos 5433 case). In both case also additional 5th PHY (MIPI CSIS 2) has been added. Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
51 lines
1.7 KiB
C
51 lines
1.7 KiB
C
/*
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* Exynos5 SoC series Power Management Unit (PMU) register offsets
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* and bit definitions.
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*
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* Copyright (C) 2014 Samsung Electronics Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_
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#define _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_
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/* Exynos5 PMU register definitions */
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#define EXYNOS5_HDMI_PHY_CONTROL (0x700)
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#define EXYNOS5_USBDRD_PHY_CONTROL (0x704)
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/* Exynos5250 specific register definitions */
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#define EXYNOS5_USBHOST_PHY_CONTROL (0x708)
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#define EXYNOS5_EFNAND_PHY_CONTROL (0x70c)
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#define EXYNOS5_MIPI_PHY0_CONTROL (0x710)
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#define EXYNOS5_MIPI_PHY1_CONTROL (0x714)
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#define EXYNOS5_ADC_PHY_CONTROL (0x718)
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#define EXYNOS5_MTCADC_PHY_CONTROL (0x71c)
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#define EXYNOS5_DPTX_PHY_CONTROL (0x720)
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#define EXYNOS5_SATA_PHY_CONTROL (0x724)
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/* Exynos5420 specific register definitions */
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#define EXYNOS5420_USBDRD1_PHY_CONTROL (0x708)
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#define EXYNOS5420_USBHOST_PHY_CONTROL (0x70c)
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#define EXYNOS5420_MIPI_PHY0_CONTROL (0x714)
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#define EXYNOS5420_MIPI_PHY1_CONTROL (0x718)
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#define EXYNOS5420_MIPI_PHY2_CONTROL (0x71c)
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#define EXYNOS5420_ADC_PHY_CONTROL (0x720)
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#define EXYNOS5420_MTCADC_PHY_CONTROL (0x724)
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#define EXYNOS5420_DPTX_PHY_CONTROL (0x728)
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/* Exynos5433 specific register definitions */
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#define EXYNOS5433_USBHOST30_PHY_CONTROL (0x728)
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#define EXYNOS5433_MIPI_PHY0_CONTROL (0x710)
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#define EXYNOS5433_MIPI_PHY1_CONTROL (0x714)
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#define EXYNOS5433_MIPI_PHY2_CONTROL (0x718)
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#define EXYNOS5_PHY_ENABLE BIT(0)
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#define EXYNOS5_MIPI_PHY_S_RESETN BIT(1)
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#define EXYNOS5_MIPI_PHY_M_RESETN BIT(2)
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#endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ */
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