mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
828f3e18e1
These are updates to SoC specific drivers that did not have another subsystem maintainer tree to go through for some reason: - Some bus and memory drivers for the MIPS P5600 based Baikal-T1 SoC that is getting added through the MIPS tree. - There are new soc_device identification drivers for TI K3, Qualcomm MSM8939 - New reset controller drivers for NXP i.MX8MP, Renesas RZ/G1H, and Hisilicon hi6220 - The SCMI firmware interface can now work across ARM SMC/HVC as a transport. - Mediatek platforms now use a new driver for their "MMSYS" hardware block that controls clocks and some other aspects in behalf of the media and gpu drivers. - Some Tegra processors have improved power management support, including getting woken up by the PMIC and cluster power down during idle. - A new v4l staging driver for Tegra is added. - Cleanups and minor bugfixes for TI, NXP, Hisilicon, Mediatek, and Tegra. Signed-off-by: Arnd Bergmann <arnd@arndb.de> -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEo6/YBQwIrVS28WGKmmx57+YAGNkFAl7XvgAACgkQmmx57+YA GNmj/hAAnAJ/hYehLfgCe711HUntgeRkaoTVpCt8BJNMdxsa23sn3V6k5+WYn1uG PtlgpefZEMHLUEEVDegR4nZXLG0Pzu1SR12KW34YPcQKkNo/+vlQ9zYUajnJ/KX6 10zdLSIzHfk1VtXKvvQQ8xFyE+S/trGmjC57E6gfoCUT3rl1maD+ccVXUBaz9oob wuMxGXQAl57mio5yT1OfSk6Fev39xRE2dN1hzP7KUYhsemZajBwBBW5wVJZCsCB8 LCGmxVkavM7BV4r2NokbBDs5rlfedBl/P/IPd9Is5a5tuGUkSsVRG9zqShxYLGM3 S06az6POQFwXKFJoUKW0dK/Koy0D7BK+vhUBPzFv4HZ8iDCVf6Jju2MJ02GMqHPj OOrXaCbLYrvN/edVUWeeFywqwMbYTRwC4DxyTq5m7HxEB004xTOhs0rX5aR0u4n1 bbsR97LguolwH9iEMzd3F3jCiKBcMecH3lAh5WcrtwlFIRrNhbWoGDoA/4TuORFS b11rgsTRIJ5Vc++D1HnSnx0ZZvUzyluMvygdALnSgVah6xYe6KVw9Kg/wioAJ04G uSTidqP3qRhsyET2HQo7CxdVfZbKfP25iKCKrdhQziztKvhF8qrUmZKloXOodRw+ ewYSRmv8c324OYYit1X43oAdW8dntq1XbSIauaqxEb4JC7x/xRY= =44Jc -----END PGP SIGNATURE----- Merge tag 'arm-drivers-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM/SoC driver updates from Arnd Bergmann: "These are updates to SoC specific drivers that did not have another subsystem maintainer tree to go through for some reason: - Some bus and memory drivers for the MIPS P5600 based Baikal-T1 SoC that is getting added through the MIPS tree. - There are new soc_device identification drivers for TI K3, Qualcomm MSM8939 - New reset controller drivers for NXP i.MX8MP, Renesas RZ/G1H, and Hisilicon hi6220 - The SCMI firmware interface can now work across ARM SMC/HVC as a transport. - Mediatek platforms now use a new driver for their "MMSYS" hardware block that controls clocks and some other aspects in behalf of the media and gpu drivers. - Some Tegra processors have improved power management support, including getting woken up by the PMIC and cluster power down during idle. - A new v4l staging driver for Tegra is added. - Cleanups and minor bugfixes for TI, NXP, Hisilicon, Mediatek, and Tegra" * tag 'arm-drivers-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (155 commits) clk: sprd: fix compile-testing bus: bt1-axi: Build the driver into the kernel bus: bt1-apb: Build the driver into the kernel bus: bt1-axi: Use sysfs_streq instead of strncmp bus: bt1-axi: Optimize the return points in the driver bus: bt1-apb: Use sysfs_streq instead of strncmp bus: bt1-apb: Use PTR_ERR_OR_ZERO to return from request-regs method bus: bt1-apb: Fix show/store callback identations bus: bt1-apb: Include linux/io.h dt-bindings: memory: Add Baikal-T1 L2-cache Control Block binding memory: Add Baikal-T1 L2-cache Control Block driver bus: Add Baikal-T1 APB-bus driver bus: Add Baikal-T1 AXI-bus driver dt-bindings: bus: Add Baikal-T1 APB-bus binding dt-bindings: bus: Add Baikal-T1 AXI-bus binding staging: tegra-video: fix V4L2 dependency tee: fix crypto select drivers: soc: ti: knav_qmss_queue: Make knav_gp_range_ops static soc: ti: add k3 platforms chipid module driver dt-bindings: soc: ti: add binding for k3 platforms chipid module ...
831 lines
21 KiB
C
831 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: Jie Qiu <jie.qiu@mediatek.com>
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*/
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_gpio.h>
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#include <linux/of_graph.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include <video/videomode.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_of.h>
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#include <drm/drm_simple_kms_helper.h>
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#include "mtk_dpi_regs.h"
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#include "mtk_drm_ddp_comp.h"
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enum mtk_dpi_out_bit_num {
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MTK_DPI_OUT_BIT_NUM_8BITS,
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MTK_DPI_OUT_BIT_NUM_10BITS,
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MTK_DPI_OUT_BIT_NUM_12BITS,
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MTK_DPI_OUT_BIT_NUM_16BITS
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};
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enum mtk_dpi_out_yc_map {
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MTK_DPI_OUT_YC_MAP_RGB,
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MTK_DPI_OUT_YC_MAP_CYCY,
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MTK_DPI_OUT_YC_MAP_YCYC,
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MTK_DPI_OUT_YC_MAP_CY,
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MTK_DPI_OUT_YC_MAP_YC
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};
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enum mtk_dpi_out_channel_swap {
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MTK_DPI_OUT_CHANNEL_SWAP_RGB,
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MTK_DPI_OUT_CHANNEL_SWAP_GBR,
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MTK_DPI_OUT_CHANNEL_SWAP_BRG,
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MTK_DPI_OUT_CHANNEL_SWAP_RBG,
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MTK_DPI_OUT_CHANNEL_SWAP_GRB,
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MTK_DPI_OUT_CHANNEL_SWAP_BGR
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};
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enum mtk_dpi_out_color_format {
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MTK_DPI_COLOR_FORMAT_RGB,
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MTK_DPI_COLOR_FORMAT_RGB_FULL,
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MTK_DPI_COLOR_FORMAT_YCBCR_444,
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MTK_DPI_COLOR_FORMAT_YCBCR_422,
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MTK_DPI_COLOR_FORMAT_XV_YCC,
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MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL,
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MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL
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};
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struct mtk_dpi {
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struct mtk_ddp_comp ddp_comp;
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struct drm_encoder encoder;
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struct drm_bridge *bridge;
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void __iomem *regs;
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struct device *dev;
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struct clk *engine_clk;
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struct clk *pixel_clk;
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struct clk *tvd_clk;
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int irq;
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struct drm_display_mode mode;
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const struct mtk_dpi_conf *conf;
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enum mtk_dpi_out_color_format color_format;
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enum mtk_dpi_out_yc_map yc_map;
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enum mtk_dpi_out_bit_num bit_num;
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enum mtk_dpi_out_channel_swap channel_swap;
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struct pinctrl *pinctrl;
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struct pinctrl_state *pins_gpio;
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struct pinctrl_state *pins_dpi;
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int refcount;
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};
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static inline struct mtk_dpi *mtk_dpi_from_encoder(struct drm_encoder *e)
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{
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return container_of(e, struct mtk_dpi, encoder);
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}
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enum mtk_dpi_polarity {
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MTK_DPI_POLARITY_RISING,
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MTK_DPI_POLARITY_FALLING,
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};
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struct mtk_dpi_polarities {
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enum mtk_dpi_polarity de_pol;
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enum mtk_dpi_polarity ck_pol;
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enum mtk_dpi_polarity hsync_pol;
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enum mtk_dpi_polarity vsync_pol;
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};
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struct mtk_dpi_sync_param {
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u32 sync_width;
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u32 front_porch;
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u32 back_porch;
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bool shift_half_line;
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};
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struct mtk_dpi_yc_limit {
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u16 y_top;
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u16 y_bottom;
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u16 c_top;
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u16 c_bottom;
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};
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struct mtk_dpi_conf {
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unsigned int (*cal_factor)(int clock);
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u32 reg_h_fre_con;
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bool edge_sel_en;
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};
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static void mtk_dpi_mask(struct mtk_dpi *dpi, u32 offset, u32 val, u32 mask)
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{
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u32 tmp = readl(dpi->regs + offset) & ~mask;
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tmp |= (val & mask);
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writel(tmp, dpi->regs + offset);
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}
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static void mtk_dpi_sw_reset(struct mtk_dpi *dpi, bool reset)
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{
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mtk_dpi_mask(dpi, DPI_RET, reset ? RST : 0, RST);
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}
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static void mtk_dpi_enable(struct mtk_dpi *dpi)
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{
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mtk_dpi_mask(dpi, DPI_EN, EN, EN);
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}
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static void mtk_dpi_disable(struct mtk_dpi *dpi)
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{
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mtk_dpi_mask(dpi, DPI_EN, 0, EN);
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}
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static void mtk_dpi_config_hsync(struct mtk_dpi *dpi,
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struct mtk_dpi_sync_param *sync)
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{
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mtk_dpi_mask(dpi, DPI_TGEN_HWIDTH,
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sync->sync_width << HPW, HPW_MASK);
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mtk_dpi_mask(dpi, DPI_TGEN_HPORCH,
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sync->back_porch << HBP, HBP_MASK);
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mtk_dpi_mask(dpi, DPI_TGEN_HPORCH, sync->front_porch << HFP,
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HFP_MASK);
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}
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static void mtk_dpi_config_vsync(struct mtk_dpi *dpi,
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struct mtk_dpi_sync_param *sync,
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u32 width_addr, u32 porch_addr)
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{
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mtk_dpi_mask(dpi, width_addr,
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sync->sync_width << VSYNC_WIDTH_SHIFT,
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VSYNC_WIDTH_MASK);
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mtk_dpi_mask(dpi, width_addr,
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sync->shift_half_line << VSYNC_HALF_LINE_SHIFT,
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VSYNC_HALF_LINE_MASK);
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mtk_dpi_mask(dpi, porch_addr,
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sync->back_porch << VSYNC_BACK_PORCH_SHIFT,
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VSYNC_BACK_PORCH_MASK);
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mtk_dpi_mask(dpi, porch_addr,
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sync->front_porch << VSYNC_FRONT_PORCH_SHIFT,
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VSYNC_FRONT_PORCH_MASK);
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}
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static void mtk_dpi_config_vsync_lodd(struct mtk_dpi *dpi,
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struct mtk_dpi_sync_param *sync)
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{
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mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH, DPI_TGEN_VPORCH);
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}
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static void mtk_dpi_config_vsync_leven(struct mtk_dpi *dpi,
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struct mtk_dpi_sync_param *sync)
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{
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mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_LEVEN,
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DPI_TGEN_VPORCH_LEVEN);
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}
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static void mtk_dpi_config_vsync_rodd(struct mtk_dpi *dpi,
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struct mtk_dpi_sync_param *sync)
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{
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mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_RODD,
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DPI_TGEN_VPORCH_RODD);
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}
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static void mtk_dpi_config_vsync_reven(struct mtk_dpi *dpi,
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struct mtk_dpi_sync_param *sync)
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{
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mtk_dpi_config_vsync(dpi, sync, DPI_TGEN_VWIDTH_REVEN,
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DPI_TGEN_VPORCH_REVEN);
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}
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static void mtk_dpi_config_pol(struct mtk_dpi *dpi,
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struct mtk_dpi_polarities *dpi_pol)
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{
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unsigned int pol;
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pol = (dpi_pol->ck_pol == MTK_DPI_POLARITY_RISING ? 0 : CK_POL) |
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(dpi_pol->de_pol == MTK_DPI_POLARITY_RISING ? 0 : DE_POL) |
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(dpi_pol->hsync_pol == MTK_DPI_POLARITY_RISING ? 0 : HSYNC_POL) |
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(dpi_pol->vsync_pol == MTK_DPI_POLARITY_RISING ? 0 : VSYNC_POL);
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mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, pol,
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CK_POL | DE_POL | HSYNC_POL | VSYNC_POL);
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}
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static void mtk_dpi_config_3d(struct mtk_dpi *dpi, bool en_3d)
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{
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mtk_dpi_mask(dpi, DPI_CON, en_3d ? TDFP_EN : 0, TDFP_EN);
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}
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static void mtk_dpi_config_interface(struct mtk_dpi *dpi, bool inter)
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{
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mtk_dpi_mask(dpi, DPI_CON, inter ? INTL_EN : 0, INTL_EN);
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}
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static void mtk_dpi_config_fb_size(struct mtk_dpi *dpi, u32 width, u32 height)
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{
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mtk_dpi_mask(dpi, DPI_SIZE, width << HSIZE, HSIZE_MASK);
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mtk_dpi_mask(dpi, DPI_SIZE, height << VSIZE, VSIZE_MASK);
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}
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static void mtk_dpi_config_channel_limit(struct mtk_dpi *dpi,
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struct mtk_dpi_yc_limit *limit)
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{
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mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_bottom << Y_LIMINT_BOT,
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Y_LIMINT_BOT_MASK);
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mtk_dpi_mask(dpi, DPI_Y_LIMIT, limit->y_top << Y_LIMINT_TOP,
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Y_LIMINT_TOP_MASK);
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mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_bottom << C_LIMIT_BOT,
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C_LIMIT_BOT_MASK);
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mtk_dpi_mask(dpi, DPI_C_LIMIT, limit->c_top << C_LIMIT_TOP,
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C_LIMIT_TOP_MASK);
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}
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static void mtk_dpi_config_bit_num(struct mtk_dpi *dpi,
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enum mtk_dpi_out_bit_num num)
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{
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u32 val;
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switch (num) {
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case MTK_DPI_OUT_BIT_NUM_8BITS:
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val = OUT_BIT_8;
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break;
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case MTK_DPI_OUT_BIT_NUM_10BITS:
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val = OUT_BIT_10;
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break;
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case MTK_DPI_OUT_BIT_NUM_12BITS:
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val = OUT_BIT_12;
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break;
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case MTK_DPI_OUT_BIT_NUM_16BITS:
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val = OUT_BIT_16;
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break;
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default:
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val = OUT_BIT_8;
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break;
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}
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mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << OUT_BIT,
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OUT_BIT_MASK);
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}
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static void mtk_dpi_config_yc_map(struct mtk_dpi *dpi,
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enum mtk_dpi_out_yc_map map)
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{
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u32 val;
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switch (map) {
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case MTK_DPI_OUT_YC_MAP_RGB:
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val = YC_MAP_RGB;
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break;
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case MTK_DPI_OUT_YC_MAP_CYCY:
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val = YC_MAP_CYCY;
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break;
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case MTK_DPI_OUT_YC_MAP_YCYC:
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val = YC_MAP_YCYC;
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break;
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case MTK_DPI_OUT_YC_MAP_CY:
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val = YC_MAP_CY;
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break;
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case MTK_DPI_OUT_YC_MAP_YC:
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val = YC_MAP_YC;
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break;
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default:
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val = YC_MAP_RGB;
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break;
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}
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mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << YC_MAP, YC_MAP_MASK);
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}
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static void mtk_dpi_config_channel_swap(struct mtk_dpi *dpi,
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enum mtk_dpi_out_channel_swap swap)
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{
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u32 val;
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switch (swap) {
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case MTK_DPI_OUT_CHANNEL_SWAP_RGB:
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val = SWAP_RGB;
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break;
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case MTK_DPI_OUT_CHANNEL_SWAP_GBR:
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val = SWAP_GBR;
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break;
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case MTK_DPI_OUT_CHANNEL_SWAP_BRG:
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val = SWAP_BRG;
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break;
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case MTK_DPI_OUT_CHANNEL_SWAP_RBG:
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val = SWAP_RBG;
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break;
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case MTK_DPI_OUT_CHANNEL_SWAP_GRB:
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val = SWAP_GRB;
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break;
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case MTK_DPI_OUT_CHANNEL_SWAP_BGR:
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val = SWAP_BGR;
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break;
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default:
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val = SWAP_RGB;
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break;
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}
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mtk_dpi_mask(dpi, DPI_OUTPUT_SETTING, val << CH_SWAP, CH_SWAP_MASK);
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}
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static void mtk_dpi_config_yuv422_enable(struct mtk_dpi *dpi, bool enable)
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{
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mtk_dpi_mask(dpi, DPI_CON, enable ? YUV422_EN : 0, YUV422_EN);
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}
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static void mtk_dpi_config_csc_enable(struct mtk_dpi *dpi, bool enable)
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{
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mtk_dpi_mask(dpi, DPI_CON, enable ? CSC_ENABLE : 0, CSC_ENABLE);
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}
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static void mtk_dpi_config_swap_input(struct mtk_dpi *dpi, bool enable)
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{
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mtk_dpi_mask(dpi, DPI_CON, enable ? IN_RB_SWAP : 0, IN_RB_SWAP);
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}
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static void mtk_dpi_config_2n_h_fre(struct mtk_dpi *dpi)
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{
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mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, H_FRE_2N, H_FRE_2N);
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}
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static void mtk_dpi_config_disable_edge(struct mtk_dpi *dpi)
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{
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if (dpi->conf->edge_sel_en)
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mtk_dpi_mask(dpi, dpi->conf->reg_h_fre_con, 0, EDGE_SEL_EN);
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}
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static void mtk_dpi_config_color_format(struct mtk_dpi *dpi,
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enum mtk_dpi_out_color_format format)
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{
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if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_444) ||
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(format == MTK_DPI_COLOR_FORMAT_YCBCR_444_FULL)) {
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mtk_dpi_config_yuv422_enable(dpi, false);
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mtk_dpi_config_csc_enable(dpi, true);
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mtk_dpi_config_swap_input(dpi, false);
|
|
mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_BGR);
|
|
} else if ((format == MTK_DPI_COLOR_FORMAT_YCBCR_422) ||
|
|
(format == MTK_DPI_COLOR_FORMAT_YCBCR_422_FULL)) {
|
|
mtk_dpi_config_yuv422_enable(dpi, true);
|
|
mtk_dpi_config_csc_enable(dpi, true);
|
|
mtk_dpi_config_swap_input(dpi, true);
|
|
mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB);
|
|
} else {
|
|
mtk_dpi_config_yuv422_enable(dpi, false);
|
|
mtk_dpi_config_csc_enable(dpi, false);
|
|
mtk_dpi_config_swap_input(dpi, false);
|
|
mtk_dpi_config_channel_swap(dpi, MTK_DPI_OUT_CHANNEL_SWAP_RGB);
|
|
}
|
|
}
|
|
|
|
static void mtk_dpi_power_off(struct mtk_dpi *dpi)
|
|
{
|
|
if (WARN_ON(dpi->refcount == 0))
|
|
return;
|
|
|
|
if (--dpi->refcount != 0)
|
|
return;
|
|
|
|
if (dpi->pinctrl && dpi->pins_gpio)
|
|
pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio);
|
|
|
|
mtk_dpi_disable(dpi);
|
|
clk_disable_unprepare(dpi->pixel_clk);
|
|
clk_disable_unprepare(dpi->engine_clk);
|
|
}
|
|
|
|
static int mtk_dpi_power_on(struct mtk_dpi *dpi)
|
|
{
|
|
int ret;
|
|
|
|
if (++dpi->refcount != 1)
|
|
return 0;
|
|
|
|
ret = clk_prepare_enable(dpi->engine_clk);
|
|
if (ret) {
|
|
dev_err(dpi->dev, "Failed to enable engine clock: %d\n", ret);
|
|
goto err_refcount;
|
|
}
|
|
|
|
ret = clk_prepare_enable(dpi->pixel_clk);
|
|
if (ret) {
|
|
dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret);
|
|
goto err_pixel;
|
|
}
|
|
|
|
if (dpi->pinctrl && dpi->pins_dpi)
|
|
pinctrl_select_state(dpi->pinctrl, dpi->pins_dpi);
|
|
|
|
mtk_dpi_enable(dpi);
|
|
return 0;
|
|
|
|
err_pixel:
|
|
clk_disable_unprepare(dpi->engine_clk);
|
|
err_refcount:
|
|
dpi->refcount--;
|
|
return ret;
|
|
}
|
|
|
|
static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
|
|
struct drm_display_mode *mode)
|
|
{
|
|
struct mtk_dpi_yc_limit limit;
|
|
struct mtk_dpi_polarities dpi_pol;
|
|
struct mtk_dpi_sync_param hsync;
|
|
struct mtk_dpi_sync_param vsync_lodd = { 0 };
|
|
struct mtk_dpi_sync_param vsync_leven = { 0 };
|
|
struct mtk_dpi_sync_param vsync_rodd = { 0 };
|
|
struct mtk_dpi_sync_param vsync_reven = { 0 };
|
|
struct videomode vm = { 0 };
|
|
unsigned long pll_rate;
|
|
unsigned int factor;
|
|
|
|
/* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
|
|
factor = dpi->conf->cal_factor(mode->clock);
|
|
drm_display_mode_to_videomode(mode, &vm);
|
|
pll_rate = vm.pixelclock * factor;
|
|
|
|
dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
|
|
pll_rate, vm.pixelclock);
|
|
|
|
clk_set_rate(dpi->tvd_clk, pll_rate);
|
|
pll_rate = clk_get_rate(dpi->tvd_clk);
|
|
|
|
vm.pixelclock = pll_rate / factor;
|
|
clk_set_rate(dpi->pixel_clk, vm.pixelclock);
|
|
vm.pixelclock = clk_get_rate(dpi->pixel_clk);
|
|
|
|
dev_dbg(dpi->dev, "Got PLL %lu Hz, pixel clock %lu Hz\n",
|
|
pll_rate, vm.pixelclock);
|
|
|
|
limit.c_bottom = 0x0010;
|
|
limit.c_top = 0x0FE0;
|
|
limit.y_bottom = 0x0010;
|
|
limit.y_top = 0x0FE0;
|
|
|
|
dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING;
|
|
dpi_pol.de_pol = MTK_DPI_POLARITY_RISING;
|
|
dpi_pol.hsync_pol = vm.flags & DISPLAY_FLAGS_HSYNC_HIGH ?
|
|
MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
|
|
dpi_pol.vsync_pol = vm.flags & DISPLAY_FLAGS_VSYNC_HIGH ?
|
|
MTK_DPI_POLARITY_FALLING : MTK_DPI_POLARITY_RISING;
|
|
hsync.sync_width = vm.hsync_len;
|
|
hsync.back_porch = vm.hback_porch;
|
|
hsync.front_porch = vm.hfront_porch;
|
|
hsync.shift_half_line = false;
|
|
vsync_lodd.sync_width = vm.vsync_len;
|
|
vsync_lodd.back_porch = vm.vback_porch;
|
|
vsync_lodd.front_porch = vm.vfront_porch;
|
|
vsync_lodd.shift_half_line = false;
|
|
|
|
if (vm.flags & DISPLAY_FLAGS_INTERLACED &&
|
|
mode->flags & DRM_MODE_FLAG_3D_MASK) {
|
|
vsync_leven = vsync_lodd;
|
|
vsync_rodd = vsync_lodd;
|
|
vsync_reven = vsync_lodd;
|
|
vsync_leven.shift_half_line = true;
|
|
vsync_reven.shift_half_line = true;
|
|
} else if (vm.flags & DISPLAY_FLAGS_INTERLACED &&
|
|
!(mode->flags & DRM_MODE_FLAG_3D_MASK)) {
|
|
vsync_leven = vsync_lodd;
|
|
vsync_leven.shift_half_line = true;
|
|
} else if (!(vm.flags & DISPLAY_FLAGS_INTERLACED) &&
|
|
mode->flags & DRM_MODE_FLAG_3D_MASK) {
|
|
vsync_rodd = vsync_lodd;
|
|
}
|
|
mtk_dpi_sw_reset(dpi, true);
|
|
mtk_dpi_config_pol(dpi, &dpi_pol);
|
|
|
|
mtk_dpi_config_hsync(dpi, &hsync);
|
|
mtk_dpi_config_vsync_lodd(dpi, &vsync_lodd);
|
|
mtk_dpi_config_vsync_rodd(dpi, &vsync_rodd);
|
|
mtk_dpi_config_vsync_leven(dpi, &vsync_leven);
|
|
mtk_dpi_config_vsync_reven(dpi, &vsync_reven);
|
|
|
|
mtk_dpi_config_3d(dpi, !!(mode->flags & DRM_MODE_FLAG_3D_MASK));
|
|
mtk_dpi_config_interface(dpi, !!(vm.flags &
|
|
DISPLAY_FLAGS_INTERLACED));
|
|
if (vm.flags & DISPLAY_FLAGS_INTERLACED)
|
|
mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive >> 1);
|
|
else
|
|
mtk_dpi_config_fb_size(dpi, vm.hactive, vm.vactive);
|
|
|
|
mtk_dpi_config_channel_limit(dpi, &limit);
|
|
mtk_dpi_config_bit_num(dpi, dpi->bit_num);
|
|
mtk_dpi_config_channel_swap(dpi, dpi->channel_swap);
|
|
mtk_dpi_config_yc_map(dpi, dpi->yc_map);
|
|
mtk_dpi_config_color_format(dpi, dpi->color_format);
|
|
mtk_dpi_config_2n_h_fre(dpi);
|
|
mtk_dpi_config_disable_edge(dpi);
|
|
mtk_dpi_sw_reset(dpi, false);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool mtk_dpi_encoder_mode_fixup(struct drm_encoder *encoder,
|
|
const struct drm_display_mode *mode,
|
|
struct drm_display_mode *adjusted_mode)
|
|
{
|
|
return true;
|
|
}
|
|
|
|
static void mtk_dpi_encoder_mode_set(struct drm_encoder *encoder,
|
|
struct drm_display_mode *mode,
|
|
struct drm_display_mode *adjusted_mode)
|
|
{
|
|
struct mtk_dpi *dpi = mtk_dpi_from_encoder(encoder);
|
|
|
|
drm_mode_copy(&dpi->mode, adjusted_mode);
|
|
}
|
|
|
|
static void mtk_dpi_encoder_disable(struct drm_encoder *encoder)
|
|
{
|
|
struct mtk_dpi *dpi = mtk_dpi_from_encoder(encoder);
|
|
|
|
mtk_dpi_power_off(dpi);
|
|
}
|
|
|
|
static void mtk_dpi_encoder_enable(struct drm_encoder *encoder)
|
|
{
|
|
struct mtk_dpi *dpi = mtk_dpi_from_encoder(encoder);
|
|
|
|
mtk_dpi_power_on(dpi);
|
|
mtk_dpi_set_display_mode(dpi, &dpi->mode);
|
|
}
|
|
|
|
static int mtk_dpi_atomic_check(struct drm_encoder *encoder,
|
|
struct drm_crtc_state *crtc_state,
|
|
struct drm_connector_state *conn_state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static const struct drm_encoder_helper_funcs mtk_dpi_encoder_helper_funcs = {
|
|
.mode_fixup = mtk_dpi_encoder_mode_fixup,
|
|
.mode_set = mtk_dpi_encoder_mode_set,
|
|
.disable = mtk_dpi_encoder_disable,
|
|
.enable = mtk_dpi_encoder_enable,
|
|
.atomic_check = mtk_dpi_atomic_check,
|
|
};
|
|
|
|
static void mtk_dpi_start(struct mtk_ddp_comp *comp)
|
|
{
|
|
struct mtk_dpi *dpi = container_of(comp, struct mtk_dpi, ddp_comp);
|
|
|
|
mtk_dpi_power_on(dpi);
|
|
}
|
|
|
|
static void mtk_dpi_stop(struct mtk_ddp_comp *comp)
|
|
{
|
|
struct mtk_dpi *dpi = container_of(comp, struct mtk_dpi, ddp_comp);
|
|
|
|
mtk_dpi_power_off(dpi);
|
|
}
|
|
|
|
static const struct mtk_ddp_comp_funcs mtk_dpi_funcs = {
|
|
.start = mtk_dpi_start,
|
|
.stop = mtk_dpi_stop,
|
|
};
|
|
|
|
static int mtk_dpi_bind(struct device *dev, struct device *master, void *data)
|
|
{
|
|
struct mtk_dpi *dpi = dev_get_drvdata(dev);
|
|
struct drm_device *drm_dev = data;
|
|
int ret;
|
|
|
|
ret = mtk_ddp_comp_register(drm_dev, &dpi->ddp_comp);
|
|
if (ret < 0) {
|
|
dev_err(dev, "Failed to register component %pOF: %d\n",
|
|
dev->of_node, ret);
|
|
return ret;
|
|
}
|
|
|
|
ret = drm_simple_encoder_init(drm_dev, &dpi->encoder,
|
|
DRM_MODE_ENCODER_TMDS);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to initialize decoder: %d\n", ret);
|
|
goto err_unregister;
|
|
}
|
|
drm_encoder_helper_add(&dpi->encoder, &mtk_dpi_encoder_helper_funcs);
|
|
|
|
/* Currently DPI0 is fixed to be driven by OVL1 */
|
|
dpi->encoder.possible_crtcs = BIT(1);
|
|
|
|
ret = drm_bridge_attach(&dpi->encoder, dpi->bridge, NULL, 0);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to attach bridge: %d\n", ret);
|
|
goto err_cleanup;
|
|
}
|
|
|
|
dpi->bit_num = MTK_DPI_OUT_BIT_NUM_8BITS;
|
|
dpi->channel_swap = MTK_DPI_OUT_CHANNEL_SWAP_RGB;
|
|
dpi->yc_map = MTK_DPI_OUT_YC_MAP_RGB;
|
|
dpi->color_format = MTK_DPI_COLOR_FORMAT_RGB;
|
|
|
|
return 0;
|
|
|
|
err_cleanup:
|
|
drm_encoder_cleanup(&dpi->encoder);
|
|
err_unregister:
|
|
mtk_ddp_comp_unregister(drm_dev, &dpi->ddp_comp);
|
|
return ret;
|
|
}
|
|
|
|
static void mtk_dpi_unbind(struct device *dev, struct device *master,
|
|
void *data)
|
|
{
|
|
struct mtk_dpi *dpi = dev_get_drvdata(dev);
|
|
struct drm_device *drm_dev = data;
|
|
|
|
drm_encoder_cleanup(&dpi->encoder);
|
|
mtk_ddp_comp_unregister(drm_dev, &dpi->ddp_comp);
|
|
}
|
|
|
|
static const struct component_ops mtk_dpi_component_ops = {
|
|
.bind = mtk_dpi_bind,
|
|
.unbind = mtk_dpi_unbind,
|
|
};
|
|
|
|
static unsigned int mt8173_calculate_factor(int clock)
|
|
{
|
|
if (clock <= 27000)
|
|
return 3 << 4;
|
|
else if (clock <= 84000)
|
|
return 3 << 3;
|
|
else if (clock <= 167000)
|
|
return 3 << 2;
|
|
else
|
|
return 3 << 1;
|
|
}
|
|
|
|
static unsigned int mt2701_calculate_factor(int clock)
|
|
{
|
|
if (clock <= 64000)
|
|
return 4;
|
|
else if (clock <= 128000)
|
|
return 2;
|
|
else
|
|
return 1;
|
|
}
|
|
|
|
static unsigned int mt8183_calculate_factor(int clock)
|
|
{
|
|
if (clock <= 27000)
|
|
return 8;
|
|
else if (clock <= 167000)
|
|
return 4;
|
|
else
|
|
return 2;
|
|
}
|
|
|
|
static const struct mtk_dpi_conf mt8173_conf = {
|
|
.cal_factor = mt8173_calculate_factor,
|
|
.reg_h_fre_con = 0xe0,
|
|
};
|
|
|
|
static const struct mtk_dpi_conf mt2701_conf = {
|
|
.cal_factor = mt2701_calculate_factor,
|
|
.reg_h_fre_con = 0xb0,
|
|
.edge_sel_en = true,
|
|
};
|
|
|
|
static const struct mtk_dpi_conf mt8183_conf = {
|
|
.cal_factor = mt8183_calculate_factor,
|
|
.reg_h_fre_con = 0xe0,
|
|
};
|
|
|
|
static int mtk_dpi_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct mtk_dpi *dpi;
|
|
struct resource *mem;
|
|
int comp_id;
|
|
int ret;
|
|
|
|
dpi = devm_kzalloc(dev, sizeof(*dpi), GFP_KERNEL);
|
|
if (!dpi)
|
|
return -ENOMEM;
|
|
|
|
dpi->dev = dev;
|
|
dpi->conf = (struct mtk_dpi_conf *)of_device_get_match_data(dev);
|
|
|
|
dpi->pinctrl = devm_pinctrl_get(&pdev->dev);
|
|
if (IS_ERR(dpi->pinctrl)) {
|
|
dpi->pinctrl = NULL;
|
|
dev_dbg(&pdev->dev, "Cannot find pinctrl!\n");
|
|
}
|
|
if (dpi->pinctrl) {
|
|
dpi->pins_gpio = pinctrl_lookup_state(dpi->pinctrl, "sleep");
|
|
if (IS_ERR(dpi->pins_gpio)) {
|
|
dpi->pins_gpio = NULL;
|
|
dev_dbg(&pdev->dev, "Cannot find pinctrl idle!\n");
|
|
}
|
|
if (dpi->pins_gpio)
|
|
pinctrl_select_state(dpi->pinctrl, dpi->pins_gpio);
|
|
|
|
dpi->pins_dpi = pinctrl_lookup_state(dpi->pinctrl, "default");
|
|
if (IS_ERR(dpi->pins_dpi)) {
|
|
dpi->pins_dpi = NULL;
|
|
dev_dbg(&pdev->dev, "Cannot find pinctrl active!\n");
|
|
}
|
|
}
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
dpi->regs = devm_ioremap_resource(dev, mem);
|
|
if (IS_ERR(dpi->regs)) {
|
|
ret = PTR_ERR(dpi->regs);
|
|
dev_err(dev, "Failed to ioremap mem resource: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
dpi->engine_clk = devm_clk_get(dev, "engine");
|
|
if (IS_ERR(dpi->engine_clk)) {
|
|
ret = PTR_ERR(dpi->engine_clk);
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "Failed to get engine clock: %d\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
dpi->pixel_clk = devm_clk_get(dev, "pixel");
|
|
if (IS_ERR(dpi->pixel_clk)) {
|
|
ret = PTR_ERR(dpi->pixel_clk);
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "Failed to get pixel clock: %d\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
dpi->tvd_clk = devm_clk_get(dev, "pll");
|
|
if (IS_ERR(dpi->tvd_clk)) {
|
|
ret = PTR_ERR(dpi->tvd_clk);
|
|
if (ret != -EPROBE_DEFER)
|
|
dev_err(dev, "Failed to get tvdpll clock: %d\n", ret);
|
|
|
|
return ret;
|
|
}
|
|
|
|
dpi->irq = platform_get_irq(pdev, 0);
|
|
if (dpi->irq <= 0) {
|
|
dev_err(dev, "Failed to get irq: %d\n", dpi->irq);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ret = drm_of_find_panel_or_bridge(dev->of_node, 0, 0,
|
|
NULL, &dpi->bridge);
|
|
if (ret)
|
|
return ret;
|
|
|
|
dev_info(dev, "Found bridge node: %pOF\n", dpi->bridge->of_node);
|
|
|
|
comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DPI);
|
|
if (comp_id < 0) {
|
|
dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
|
|
return comp_id;
|
|
}
|
|
|
|
ret = mtk_ddp_comp_init(dev, dev->of_node, &dpi->ddp_comp, comp_id,
|
|
&mtk_dpi_funcs);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to initialize component: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, dpi);
|
|
|
|
ret = component_add(dev, &mtk_dpi_component_ops);
|
|
if (ret) {
|
|
dev_err(dev, "Failed to add component: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mtk_dpi_remove(struct platform_device *pdev)
|
|
{
|
|
component_del(&pdev->dev, &mtk_dpi_component_ops);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id mtk_dpi_of_ids[] = {
|
|
{ .compatible = "mediatek,mt2701-dpi",
|
|
.data = &mt2701_conf,
|
|
},
|
|
{ .compatible = "mediatek,mt8173-dpi",
|
|
.data = &mt8173_conf,
|
|
},
|
|
{ .compatible = "mediatek,mt8183-dpi",
|
|
.data = &mt8183_conf,
|
|
},
|
|
{ },
|
|
};
|
|
|
|
struct platform_driver mtk_dpi_driver = {
|
|
.probe = mtk_dpi_probe,
|
|
.remove = mtk_dpi_remove,
|
|
.driver = {
|
|
.name = "mediatek-dpi",
|
|
.of_match_table = mtk_dpi_of_ids,
|
|
},
|
|
};
|