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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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df5d6ecf81
Support for TLB reservation (or TLB Write Conditional) and Paired MAS registers are optional for a processor implementation so we handle them via MMU feature sections. We currently only used paired MAS registers to access the full RPN + perm bits that are kept in MAS7||MAS3. We assume that if an implementation has hardware page table at this time it also implements in TLB reservations. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
145 lines
4.2 KiB
C
145 lines
4.2 KiB
C
#ifndef _ASM_POWERPC_MMU_H_
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#define _ASM_POWERPC_MMU_H_
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#ifdef __KERNEL__
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#include <asm/asm-compat.h>
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#include <asm/feature-fixups.h>
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/*
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* MMU features bit definitions
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*/
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/*
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* First half is MMU families
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*/
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#define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001)
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#define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002)
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#define MMU_FTR_TYPE_40x ASM_CONST(0x00000004)
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#define MMU_FTR_TYPE_44x ASM_CONST(0x00000008)
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#define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010)
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#define MMU_FTR_TYPE_3E ASM_CONST(0x00000020)
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/*
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* This is individual features
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*/
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/* Enable use of high BAT registers */
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#define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000)
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/* Enable >32-bit physical addresses on 32-bit processor, only used
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* by CONFIG_6xx currently as BookE supports that from day 1
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*/
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#define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000)
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/* Enable use of broadcast TLB invalidations. We don't always set it
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* on processors that support it due to other constraints with the
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* use of such invalidations
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*/
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#define MMU_FTR_USE_TLBIVAX_BCAST ASM_CONST(0x00040000)
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/* Enable use of tlbilx invalidate instructions.
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*/
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#define MMU_FTR_USE_TLBILX ASM_CONST(0x00080000)
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/* This indicates that the processor cannot handle multiple outstanding
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* broadcast tlbivax or tlbsync. This makes the code use a spinlock
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* around such invalidate forms.
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*/
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#define MMU_FTR_LOCK_BCAST_INVAL ASM_CONST(0x00100000)
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/* This indicates that the processor doesn't handle way selection
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* properly and needs SW to track and update the LRU state. This
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* is specific to an errata on e300c2/c3/c4 class parts
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*/
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#define MMU_FTR_NEED_DTLB_SW_LRU ASM_CONST(0x00200000)
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/* This indicates that the processor uses the ISA 2.06 server tlbie
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* mnemonics
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*/
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#define MMU_FTR_TLBIE_206 ASM_CONST(0x00400000)
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/* Enable use of TLB reservation. Processor should support tlbsrx.
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* instruction and MAS0[WQ].
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*/
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#define MMU_FTR_USE_TLBRSRV ASM_CONST(0x00800000)
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/* Use paired MAS registers (MAS7||MAS3, etc.)
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*/
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#define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
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#ifndef __ASSEMBLY__
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#include <asm/cputable.h>
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static inline int mmu_has_feature(unsigned long feature)
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{
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return (cur_cpu_spec->mmu_features & feature);
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}
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extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup;
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/* MMU initialization (64-bit only fo now) */
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extern void early_init_mmu(void);
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extern void early_init_mmu_secondary(void);
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#endif /* !__ASSEMBLY__ */
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/* The kernel use the constants below to index in the page sizes array.
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* The use of fixed constants for this purpose is better for performances
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* of the low level hash refill handlers.
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*
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* A non supported page size has a "shift" field set to 0
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*
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* Any new page size being implemented can get a new entry in here. Whether
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* the kernel will use it or not is a different matter though. The actual page
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* size used by hugetlbfs is not defined here and may be made variable
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*
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* Note: This array ended up being a false good idea as it's growing to the
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* point where I wonder if we should replace it with something different,
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* to think about, feedback welcome. --BenH.
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*/
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/* There are #define as they have to be used in assembly
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*
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* WARNING: If you change this list, make sure to update the array of
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* names currently in arch/powerpc/mm/hugetlbpage.c or bad things will
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* happen
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*/
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#define MMU_PAGE_4K 0
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#define MMU_PAGE_16K 1
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#define MMU_PAGE_64K 2
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#define MMU_PAGE_64K_AP 3 /* "Admixed pages" (hash64 only) */
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#define MMU_PAGE_256K 4
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#define MMU_PAGE_1M 5
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#define MMU_PAGE_8M 6
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#define MMU_PAGE_16M 7
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#define MMU_PAGE_256M 8
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#define MMU_PAGE_1G 9
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#define MMU_PAGE_16G 10
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#define MMU_PAGE_64G 11
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#define MMU_PAGE_COUNT 12
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#if defined(CONFIG_PPC_STD_MMU_64)
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/* 64-bit classic hash table MMU */
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# include <asm/mmu-hash64.h>
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#elif defined(CONFIG_PPC_STD_MMU_32)
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/* 32-bit classic hash table MMU */
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# include <asm/mmu-hash32.h>
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#elif defined(CONFIG_40x)
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/* 40x-style software loaded TLB */
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# include <asm/mmu-40x.h>
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#elif defined(CONFIG_44x)
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/* 44x-style software loaded TLB */
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# include <asm/mmu-44x.h>
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#elif defined(CONFIG_PPC_BOOK3E_MMU)
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/* Freescale Book-E software loaded TLB or Book-3e (ISA 2.06+) MMU */
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# include <asm/mmu-book3e.h>
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#elif defined (CONFIG_PPC_8xx)
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/* Motorola/Freescale 8xx software loaded TLB */
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# include <asm/mmu-8xx.h>
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#endif
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_MMU_H_ */
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