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9ae0522537
The AER error injection mechanism just blindly abuses generic_handle_irq()
which is really not meant for consumption by random drivers. The include of
linux/irq.h should have been a red flag in the first place. Driver code,
unless implementing interrupt chips or low level hypervisor functionality
has absolutely no business with that.
Invoking generic_handle_irq() from non interrupt handling context can have
nasty side effects at least on x86 due to the hardware trainwreck which
makes interrupt affinity changes a fragile beast. Sathyanarayanan triggered
a NULL pointer dereference in the low level APIC code that way. While the
particular pointer could be checked this would only paper over the issue
because there are other ways to trigger warnings or silently corrupt state.
Invoke the new irq_inject_interrupt() mechanism, which has the necessary
sanity checks in place and injects the interrupt via the irq_retrigger()
mechanism, which is at least halfways safe vs. the fragile x86 affinity
change mechanics.
It's safe on x86 as it does not corrupt state, but it still can cause a
premature completion of an interrupt affinity change causing the interrupt
line to become stale. Very unlikely, but possible.
For regular operations this is a non issue as AER error injection is meant
for debugging and testing and not for usage on production systems. People
using this should better know what they are doing.
Fixes: 390e2db824 ("PCI/AER: Abstract AER interrupt handling")
Reported-by: sathyanarayanan.kuppuswamy@linux.intel.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lkml.kernel.org/r/20200306130624.098374457@linutronix.de
144 lines
3.9 KiB
Plaintext
144 lines
3.9 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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#
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# PCI Express Port Bus Configuration
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#
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config PCIEPORTBUS
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bool "PCI Express Port Bus support"
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help
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This enables PCI Express Port Bus support. Users can then enable
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support for Native Hot-Plug, Advanced Error Reporting, Power
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Management Events, and Downstream Port Containment.
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#
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# Include service Kconfig here
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#
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config HOTPLUG_PCI_PCIE
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bool "PCI Express Hotplug driver"
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depends on HOTPLUG_PCI && PCIEPORTBUS
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help
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Say Y here if you have a motherboard that supports PCI Express Native
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Hotplug
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When in doubt, say N.
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config PCIEAER
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bool "PCI Express Advanced Error Reporting support"
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depends on PCIEPORTBUS
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select RAS
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default y
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help
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This enables PCI Express Root Port Advanced Error Reporting
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(AER) driver support. Error reporting messages sent to Root
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Port will be handled by PCI Express AER driver.
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config PCIEAER_INJECT
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tristate "PCI Express error injection support"
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depends on PCIEAER
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select GENERIC_IRQ_INJECTION
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help
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This enables PCI Express Root Port Advanced Error Reporting
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(AER) software error injector.
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Debugging AER code is quite difficult because it is hard
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to trigger various real hardware errors. Software-based
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error injection can fake almost all kinds of errors with the
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help of a user space helper tool aer-inject, which can be
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gotten from:
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http://www.kernel.org/pub/linux/utils/pci/aer-inject/
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#
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# PCI Express ECRC
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#
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config PCIE_ECRC
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bool "PCI Express ECRC settings control"
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depends on PCIEAER
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help
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Used to override firmware/bios settings for PCI Express ECRC
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(transaction layer end-to-end CRC checking).
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When in doubt, say N.
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#
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# PCI Express ASPM
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#
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config PCIEASPM
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bool "PCI Express ASPM control" if EXPERT
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default y
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help
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This enables OS control over PCI Express ASPM (Active State
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Power Management) and Clock Power Management. ASPM supports
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state L0/L0s/L1.
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ASPM is initially set up by the firmware. With this option enabled,
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Linux can modify this state in order to disable ASPM on known-bad
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hardware or configurations and enable it when known-safe.
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ASPM can be disabled or enabled at runtime via
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/sys/module/pcie_aspm/parameters/policy
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When in doubt, say Y.
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choice
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prompt "Default ASPM policy"
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default PCIEASPM_DEFAULT
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depends on PCIEASPM
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config PCIEASPM_DEFAULT
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bool "BIOS default"
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depends on PCIEASPM
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help
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Use the BIOS defaults for PCI Express ASPM.
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config PCIEASPM_POWERSAVE
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bool "Powersave"
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depends on PCIEASPM
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help
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Enable PCI Express ASPM L0s and L1 where possible, even if the
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BIOS did not.
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config PCIEASPM_POWER_SUPERSAVE
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bool "Power Supersave"
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depends on PCIEASPM
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help
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Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where
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possible. This would result in higher power savings while staying in L1
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where the components support it.
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config PCIEASPM_PERFORMANCE
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bool "Performance"
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depends on PCIEASPM
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help
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Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.
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endchoice
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config PCIE_PME
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def_bool y
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depends on PCIEPORTBUS && PM
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config PCIE_DPC
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bool "PCI Express Downstream Port Containment support"
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depends on PCIEPORTBUS && PCIEAER
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help
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This enables PCI Express Downstream Port Containment (DPC)
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driver support. DPC events from Root and Downstream ports
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will be handled by the DPC driver. If your system doesn't
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have this capability or you do not want to use this feature,
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it is safe to answer N.
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config PCIE_PTM
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bool "PCI Express Precision Time Measurement support"
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help
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This enables PCI Express Precision Time Measurement (PTM)
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support.
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This is only useful if you have devices that support PTM, but it
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is safe to enable even if you don't.
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config PCIE_BW
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bool "PCI Express Bandwidth Change Notification"
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depends on PCIEPORTBUS
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help
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This enables PCI Express Bandwidth Change Notification. If
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you know link width or rate changes occur only to correct
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unreliable links, you may answer Y.
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