mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 12:15:08 +07:00
8362fd64f0
Various driver updates for platforms and a couple of the small driver
subsystems we merge through our tree:
- A driver for SCU (system control) on NXP i.MX8QXP
- Qualcomm Always-on Subsystem messaging driver (AOSS QMP)
- Qualcomm PM support for MSM8998
- Support for a newer version of DRAM PHY driver for Broadcom (DPFE)
- Reset controller support for Bitmain BM1880
- TI SCI (System Control Interface) support for CPU control on AM654
processors
- More TI sysc refactoring and rework
-----BEGIN PGP SIGNATURE-----
iQJDBAABCAAtFiEElf+HevZ4QCAJmMQ+jBrnPN6EHHcFAl0yK3YPHG9sb2ZAbGl4
b20ubmV0AAoJEIwa5zzehBx3WdUQAJEFRzY4+8VfsUspKmGwzHsrk7t1038JUEDE
VL3yYlvSGeHg5a58AI5PCR5ZCsyPK7Yw9cAcYexd0frFR7BCwKWrjqem0Lb5ovdK
CYM517DRtYPSBMF08Xw4pbZlT0yg65F1e9cf6BlUpkUZ6lJn4gUy8Y4BE6Aw/zuF
QKtQNs6Q8BUZqS3uoOpJ/PY4JiUmLPQPO4Lry7Lud8Z7qgArCC326paC3wwqjLoC
TpoMqb6izt7Vzo4BtTo5TUCyiEFZDlb/thhDySVlYRE7DQJusHBvRO9qgjI2ahOo
1/935q1fJO7S6+Yvc8DIzrD/DrIUOvOshi31F/J6iWKkQkTUxtQwsVReZKaiOfSD
fYxNVCgTcMS6ailKQSMQ0SYgXDa2gWdV3tS9XU8qML3tnDthi1nDmZks0QAAnFPS
bXRcWGtgqeQJ+QJ7yyKrsD9POeaq3Hc5/f1DN34H//Cyn0ip/fD6fkLCMIfUDwmu
TmO2Mnj6/fG/iBK+ToF+DaJ0/u3RiV2MC2vCE+0m3cVI9jtq9iA1y3UlmoaKUhhC
t9znA+u8/Jc5S2zNQriI2Ja5q8nKfihL7Jf68ENvGzLc7YuAqP6yx1LMg1g6Wshc
nLT+kHOF6DCUC3W7a8VuNyaxCwVtTbNTti+nvQVOmV6eaGiD5vzpXkHBWMbOJ7Lh
YOBwGyb4
=ek+j
-----END PGP SIGNATURE-----
Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC-related driver updates from Olof Johansson:
"Various driver updates for platforms and a couple of the small driver
subsystems we merge through our tree:
- A driver for SCU (system control) on NXP i.MX8QXP
- Qualcomm Always-on Subsystem messaging driver (AOSS QMP)
- Qualcomm PM support for MSM8998
- Support for a newer version of DRAM PHY driver for Broadcom (DPFE)
- Reset controller support for Bitmain BM1880
- TI SCI (System Control Interface) support for CPU control on AM654
processors
- More TI sysc refactoring and rework"
* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (84 commits)
reset: remove redundant null check on pointer dev
soc: rockchip: work around clang warning
dt-bindings: reset: imx7: Fix the spelling of 'indices'
soc: imx: Add i.MX8MN SoC driver support
soc: aspeed: lpc-ctrl: Fix probe error handling
soc: qcom: geni: Add support for ACPI
firmware: ti_sci: Fix gcc unused-but-set-variable warning
firmware: ti_sci: Use the correct style for SPDX License Identifier
soc: imx8: Use existing of_root directly
soc: imx8: Fix potential kernel dump in error path
firmware/psci: psci_checker: Park kthreads before stopping them
memory: move jedec_ddr.h from include/memory to drivers/memory/
memory: move jedec_ddr_data.c from lib/ to drivers/memory/
MAINTAINERS: Remove myself as qcom maintainer
soc: aspeed: lpc-ctrl: make parameter optional
soc: qcom: apr: Don't use reg for domain id
soc: qcom: fix QCOM_AOSS_QMP dependency and build errors
memory: tegra: Fix -Wunused-const-variable
firmware: tegra: Early resume BPMP
soc/tegra: Select pinctrl for Tegra194
...
134 lines
2.9 KiB
C
134 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
|
|
/*
|
|
* DDR addressing details and AC timing parameters from JEDEC specs
|
|
*
|
|
* Copyright (C) 2012 Texas Instruments, Inc.
|
|
*
|
|
* Aneesh V <aneesh@ti.com>
|
|
*/
|
|
|
|
#include <linux/export.h>
|
|
|
|
#include "jedec_ddr.h"
|
|
|
|
/* LPDDR2 addressing details from JESD209-2 section 2.4 */
|
|
const struct lpddr2_addressing
|
|
lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES] = {
|
|
{B4, T_REFI_15_6, T_RFC_90}, /* 64M */
|
|
{B4, T_REFI_15_6, T_RFC_90}, /* 128M */
|
|
{B4, T_REFI_7_8, T_RFC_90}, /* 256M */
|
|
{B4, T_REFI_7_8, T_RFC_90}, /* 512M */
|
|
{B8, T_REFI_7_8, T_RFC_130}, /* 1GS4 */
|
|
{B8, T_REFI_3_9, T_RFC_130}, /* 2GS4 */
|
|
{B8, T_REFI_3_9, T_RFC_130}, /* 4G */
|
|
{B8, T_REFI_3_9, T_RFC_210}, /* 8G */
|
|
{B4, T_REFI_7_8, T_RFC_130}, /* 1GS2 */
|
|
{B4, T_REFI_3_9, T_RFC_130}, /* 2GS2 */
|
|
};
|
|
EXPORT_SYMBOL_GPL(lpddr2_jedec_addressing_table);
|
|
|
|
/* LPDDR2 AC timing parameters from JESD209-2 section 12 */
|
|
const struct lpddr2_timings
|
|
lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES] = {
|
|
/* Speed bin 400(200 MHz) */
|
|
[0] = {
|
|
.max_freq = 200000000,
|
|
.min_freq = 10000000,
|
|
.tRPab = 21000,
|
|
.tRCD = 18000,
|
|
.tWR = 15000,
|
|
.tRAS_min = 42000,
|
|
.tRRD = 10000,
|
|
.tWTR = 10000,
|
|
.tXP = 7500,
|
|
.tRTP = 7500,
|
|
.tCKESR = 15000,
|
|
.tDQSCK_max = 5500,
|
|
.tFAW = 50000,
|
|
.tZQCS = 90000,
|
|
.tZQCL = 360000,
|
|
.tZQinit = 1000000,
|
|
.tRAS_max_ns = 70000,
|
|
.tDQSCK_max_derated = 6000,
|
|
},
|
|
/* Speed bin 533(266 MHz) */
|
|
[1] = {
|
|
.max_freq = 266666666,
|
|
.min_freq = 10000000,
|
|
.tRPab = 21000,
|
|
.tRCD = 18000,
|
|
.tWR = 15000,
|
|
.tRAS_min = 42000,
|
|
.tRRD = 10000,
|
|
.tWTR = 7500,
|
|
.tXP = 7500,
|
|
.tRTP = 7500,
|
|
.tCKESR = 15000,
|
|
.tDQSCK_max = 5500,
|
|
.tFAW = 50000,
|
|
.tZQCS = 90000,
|
|
.tZQCL = 360000,
|
|
.tZQinit = 1000000,
|
|
.tRAS_max_ns = 70000,
|
|
.tDQSCK_max_derated = 6000,
|
|
},
|
|
/* Speed bin 800(400 MHz) */
|
|
[2] = {
|
|
.max_freq = 400000000,
|
|
.min_freq = 10000000,
|
|
.tRPab = 21000,
|
|
.tRCD = 18000,
|
|
.tWR = 15000,
|
|
.tRAS_min = 42000,
|
|
.tRRD = 10000,
|
|
.tWTR = 7500,
|
|
.tXP = 7500,
|
|
.tRTP = 7500,
|
|
.tCKESR = 15000,
|
|
.tDQSCK_max = 5500,
|
|
.tFAW = 50000,
|
|
.tZQCS = 90000,
|
|
.tZQCL = 360000,
|
|
.tZQinit = 1000000,
|
|
.tRAS_max_ns = 70000,
|
|
.tDQSCK_max_derated = 6000,
|
|
},
|
|
/* Speed bin 1066(533 MHz) */
|
|
[3] = {
|
|
.max_freq = 533333333,
|
|
.min_freq = 10000000,
|
|
.tRPab = 21000,
|
|
.tRCD = 18000,
|
|
.tWR = 15000,
|
|
.tRAS_min = 42000,
|
|
.tRRD = 10000,
|
|
.tWTR = 7500,
|
|
.tXP = 7500,
|
|
.tRTP = 7500,
|
|
.tCKESR = 15000,
|
|
.tDQSCK_max = 5500,
|
|
.tFAW = 50000,
|
|
.tZQCS = 90000,
|
|
.tZQCL = 360000,
|
|
.tZQinit = 1000000,
|
|
.tRAS_max_ns = 70000,
|
|
.tDQSCK_max_derated = 5620,
|
|
},
|
|
};
|
|
EXPORT_SYMBOL_GPL(lpddr2_jedec_timings);
|
|
|
|
const struct lpddr2_min_tck lpddr2_jedec_min_tck = {
|
|
.tRPab = 3,
|
|
.tRCD = 3,
|
|
.tWR = 3,
|
|
.tRASmin = 3,
|
|
.tRRD = 2,
|
|
.tWTR = 2,
|
|
.tXP = 2,
|
|
.tRTP = 2,
|
|
.tCKE = 3,
|
|
.tCKESR = 3,
|
|
.tFAW = 8
|
|
};
|
|
EXPORT_SYMBOL_GPL(lpddr2_jedec_min_tck);
|