mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 05:55:18 +07:00
fba4e9f989
Starting with commit <8947e396a829> ("Documentation: dt: mtd:
replace "nor-jedec" binding with "jedec, spi-nor"") we have
"jedec,spi-nor" binding indicating support for JEDEC identification.
Use it for all flashes that are supposed to support READ ID op
according to the datasheets.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@freescale.com>
Signed-off-by: Scott Wood <oss@buserror.net>
281 lines
5.3 KiB
Plaintext
281 lines
5.3 KiB
Plaintext
/*
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* Device tree source for the Emerson/Artesyn MVME2500
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*
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* Copyright 2014 Elettra-Sincrotrone Trieste S.C.p.A.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* Based on: P2020 DS Device Tree Source
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* Copyright 2009 Freescale Semiconductor Inc.
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*/
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/include/ "p2020si-pre.dtsi"
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/ {
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model = "MVME2500";
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compatible = "artesyn,MVME2500";
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aliases {
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serial2 = &serial2;
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serial3 = &serial3;
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serial4 = &serial4;
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serial5 = &serial5;
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};
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memory {
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device_type = "memory";
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};
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soc: soc@ffe00000 {
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ranges = <0x0 0 0xffe00000 0x100000>;
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i2c@3000 {
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hwmon@4c {
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compatible = "adi,adt7461";
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reg = <0x4c>;
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};
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rtc@68 {
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compatible = "dallas,ds1337";
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reg = <0x68>;
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interrupts = <8 1 0 0>;
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};
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eeprom@54 {
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compatible = "atmel,24c64";
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reg = <0x54>;
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};
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eeprom@52 {
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compatible = "atmel,24c512";
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reg = <0x52>;
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};
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eeprom@53 {
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compatible = "atmel,24c512";
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reg = <0x53>;
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};
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eeprom@50 {
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compatible = "atmel,24c02";
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reg = <0x50>;
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};
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};
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spi0: spi@7000 {
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fsl,espi-num-chipselects = <2>;
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flash@0 {
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compatible = "atmel,at25df641", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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};
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flash@1 {
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compatible = "atmel,at25df641", "jedec,spi-nor";
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reg = <1>;
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spi-max-frequency = <10000000>;
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};
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};
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usb@22000 {
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dr_mode = "host";
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phy_type = "ulpi";
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};
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enet0: ethernet@24000 {
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tbi-handle = <&tbi0>;
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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};
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mdio@24520 {
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phy1: ethernet-phy@1 {
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compatible = "brcm,bcm54616S";
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interrupts = <6 1 0 0>;
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reg = <0x1>;
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};
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phy2: ethernet-phy@2 {
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compatible = "brcm,bcm54616S";
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interrupts = <6 1 0 0>;
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reg = <0x2>;
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};
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phy3: ethernet-phy@3 {
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compatible = "brcm,bcm54616S";
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interrupts = <5 1 0 0>;
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reg = <0x3>;
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};
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phy7: ethernet-phy@7 {
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compatible = "brcm,bcm54616S";
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interrupts = <7 1 0 0>;
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reg = <0x7>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet1: ethernet@25000 {
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tbi-handle = <&tbi1>;
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phy-handle = <&phy7>;
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phy-connection-type = "rgmii-id";
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};
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mdio@25520 {
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet2: ethernet@26000 {
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tbi-handle = <&tbi2>;
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phy-handle = <&phy3>;
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phy-connection-type = "rgmii-id";
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};
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mdio@26520 {
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tbi2: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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lbc: localbus@ffe05000 {
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reg = <0 0xffe05000 0 0x1000>;
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ranges = <0x0 0x0 0x0 0xfff00000 0x00080000
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0x1 0x0 0x0 0xffc40000 0x00010000
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0x2 0x0 0x0 0xffc50000 0x00010000
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0x3 0x0 0x0 0xffc60000 0x00010000
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0x4 0x0 0x0 0xffc70000 0x00010000
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0x6 0x0 0x0 0xffc80000 0x00010000
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0x5 0x0 0x0 0xffdf0000 0x00008000>;
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serial2: serial@1,0 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x1 0x0 0x100>;
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clock-frequency = <1843200>;
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interrupts = <11 2 0 0>;
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};
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serial3: serial@2,0 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x2 0x0 0x100>;
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clock-frequency = <1843200>;
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interrupts = <1 2 0 0>;
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};
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serial4: serial@3,0 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x3 0x0 0x100>;
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clock-frequency = <1843200>;
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interrupts = <2 2 0 0>;
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};
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serial5: serial@4,0 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0x4 0x0 0x100>;
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clock-frequency = <1843200>;
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interrupts = <3 2 0 0>;
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};
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mram@0,0 {
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compatible = "everspin,mram", "mtd-ram";
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reg = <0x0 0x0 0x80000>;
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bank-width = <2>;
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};
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board-control@5,0 {
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compatible = "artesyn,mvme2500-fpga";
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reg = <0x5 0x0 0x01000>;
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};
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cpld@6,0 {
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compatible = "artesyn,mvme2500-cpld";
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reg = <0x6 0x0 0x10000>;
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interrupts = <9 1 0 0>;
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};
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};
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pci0: pcie@ffe08000 {
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reg = <0 0xffe08000 0 0x1000>;
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ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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pci1: pcie@ffe09000 {
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reg = <0 0xffe09000 0 0x1000>;
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ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xa0000000
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0x2000000 0x0 0xa0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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pci2: pcie@ffe0a000 {
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reg = <0 0xffe0a000 0 0x1000>;
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ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xc0000000
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0x2000000 0x0 0xc0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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};
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/include/ "p2020si-post.dtsi"
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/ {
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soc@ffe00000 {
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serial@4600 {
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status = "disabled";
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};
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i2c@3100 {
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status = "disabled";
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};
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sdhc@2e000 {
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compatible = "fsl,p2020-esdhc", "fsl,esdhc";
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non-removable;
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};
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};
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};
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