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5224644551
To make provision for more than one L2 caches in the system, change the name from L2 to L2_1; same as in T4 platforms. * Also remove the L2 entry from common file "arch/powerpc/boot/dts/fsl/b4si-post.dtsi" Keep them only in separate files for b4860 and b4420. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
98 lines
3.3 KiB
Plaintext
98 lines
3.3 KiB
Plaintext
/*
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* B4420 Silicon/SoC Device Tree Source (post include)
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*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* This software is provided by Freescale Semiconductor "as is" and any
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* express or implied warranties, including, but not limited to, the implied
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* warranties of merchantability and fitness for a particular purpose are
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* disclaimed. In no event shall Freescale Semiconductor be liable for any
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* direct, indirect, incidental, special, exemplary, or consequential damages
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* (including, but not limited to, procurement of substitute goods or services;
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* loss of use, data, or profits; or business interruption) however caused and
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* on any theory of liability, whether in contract, strict liability, or tort
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* (including negligence or otherwise) arising in any way out of the use of
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* this software, even if advised of the possibility of such damage.
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*/
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/include/ "b4si-post.dtsi"
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/* controller at 0x200000 */
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&pci0 {
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compatible = "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4";
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};
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&dcsr {
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dcsr-epu@0 {
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compatible = "fsl,b4420-dcsr-epu", "fsl,dcsr-epu";
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};
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dcsr-npc {
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compatible = "fsl,b4420-dcsr-cnpc", "fsl,dcsr-cnpc";
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};
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dcsr-dpaa@9000 {
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compatible = "fsl,b4420-dcsr-dpaa", "fsl,dcsr-dpaa";
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};
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dcsr-ocn@11000 {
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compatible = "fsl,b4420-dcsr-ocn", "fsl,dcsr-ocn";
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};
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dcsr-nal@18000 {
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compatible = "fsl,b4420-dcsr-nal", "fsl,dcsr-nal";
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};
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dcsr-rcpm@22000 {
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compatible = "fsl,b4420-dcsr-rcpm", "fsl,dcsr-rcpm";
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};
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dcsr-snpc@30000 {
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compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
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};
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dcsr-snpc@31000 {
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compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
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};
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dcsr-cpu-sb-proxy@108000 {
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compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu1>;
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reg = <0x108000 0x1000 0x109000 0x1000>;
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};
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};
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&soc {
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cpc: l3-cache-controller@10000 {
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compatible = "fsl,b4420-l3-cache-controller", "cache";
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};
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guts: global-utilities@e0000 {
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compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
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};
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global-utilities@e1000 {
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compatible = "fsl,b4420-clockgen", "fsl,b4-clockgen",
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"fsl,qoriq-clockgen-2.0";
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};
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rcpm: global-utilities@e2000 {
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compatible = "fsl,b4420-rcpm", "fsl,qoriq-rcpm-2.0";
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};
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L2_1: l2-cache-controller@c20000 {
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compatible = "fsl,b4420-l2-cache-controller";
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reg = <0xc20000 0x40000>;
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next-level-cache = <&cpc>;
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};
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};
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