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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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2d888f48e0
Emulate deprecated 'setend' instruction for AArch32 bit tasks. setend [le/be] - Sets the endianness of EL0 On systems with CPUs which support mixed endian at EL0, the hardware support for the instruction can be enabled by setting the SCTLR_EL1.SED bit. Like the other emulated instructions it is controlled by an entry in /proc/sys/abi/. For more information see : Documentation/arm64/legacy_instructions.txt The instruction is emulated by setting/clearing the SPSR_EL1.E bit, which will be reflected in the PSTATE.E in AArch32 context. This patch also restores the native endianness for the execution of signal handlers, since the process could have changed the endianness. Note: All CPUs on the system must have mixed endian support at EL0. Once the handler is registered, hotplugging a CPU which doesn't support mixed endian, could lead to unexpected results/behavior in applications. Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Punit Agrawal <punit.agrawal@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
194 lines
5.2 KiB
C
194 lines
5.2 KiB
C
/*
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* Based on arch/arm/include/asm/ptrace.h
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*
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* Copyright (C) 1996-2003 Russell King
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_PTRACE_H
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#define __ASM_PTRACE_H
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#include <uapi/asm/ptrace.h>
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/* Current Exception Level values, as contained in CurrentEL */
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#define CurrentEL_EL1 (1 << 2)
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#define CurrentEL_EL2 (2 << 2)
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/* AArch32-specific ptrace requests */
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#define COMPAT_PTRACE_GETREGS 12
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#define COMPAT_PTRACE_SETREGS 13
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#define COMPAT_PTRACE_GET_THREAD_AREA 22
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#define COMPAT_PTRACE_SET_SYSCALL 23
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#define COMPAT_PTRACE_GETVFPREGS 27
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#define COMPAT_PTRACE_SETVFPREGS 28
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#define COMPAT_PTRACE_GETHBPREGS 29
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#define COMPAT_PTRACE_SETHBPREGS 30
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/* AArch32 CPSR bits */
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#define COMPAT_PSR_MODE_MASK 0x0000001f
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#define COMPAT_PSR_MODE_USR 0x00000010
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#define COMPAT_PSR_MODE_FIQ 0x00000011
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#define COMPAT_PSR_MODE_IRQ 0x00000012
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#define COMPAT_PSR_MODE_SVC 0x00000013
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#define COMPAT_PSR_MODE_ABT 0x00000017
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#define COMPAT_PSR_MODE_HYP 0x0000001a
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#define COMPAT_PSR_MODE_UND 0x0000001b
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#define COMPAT_PSR_MODE_SYS 0x0000001f
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#define COMPAT_PSR_T_BIT 0x00000020
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#define COMPAT_PSR_E_BIT 0x00000200
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#define COMPAT_PSR_F_BIT 0x00000040
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#define COMPAT_PSR_I_BIT 0x00000080
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#define COMPAT_PSR_A_BIT 0x00000100
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#define COMPAT_PSR_E_BIT 0x00000200
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#define COMPAT_PSR_J_BIT 0x01000000
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#define COMPAT_PSR_Q_BIT 0x08000000
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#define COMPAT_PSR_V_BIT 0x10000000
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#define COMPAT_PSR_C_BIT 0x20000000
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#define COMPAT_PSR_Z_BIT 0x40000000
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#define COMPAT_PSR_N_BIT 0x80000000
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#define COMPAT_PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */
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#ifdef CONFIG_CPU_BIG_ENDIAN
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#define COMPAT_PSR_ENDSTATE COMPAT_PSR_E_BIT
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#else
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#define COMPAT_PSR_ENDSTATE 0
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#endif
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/*
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* These are 'magic' values for PTRACE_PEEKUSR that return info about where a
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* process is located in memory.
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*/
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#define COMPAT_PT_TEXT_ADDR 0x10000
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#define COMPAT_PT_DATA_ADDR 0x10004
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#define COMPAT_PT_TEXT_END_ADDR 0x10008
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#ifndef __ASSEMBLY__
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/* sizeof(struct user) for AArch32 */
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#define COMPAT_USER_SZ 296
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/* Architecturally defined mapping between AArch32 and AArch64 registers */
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#define compat_usr(x) regs[(x)]
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#define compat_fp regs[11]
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#define compat_sp regs[13]
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#define compat_lr regs[14]
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#define compat_sp_hyp regs[15]
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#define compat_sp_irq regs[16]
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#define compat_lr_irq regs[17]
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#define compat_sp_svc regs[18]
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#define compat_lr_svc regs[19]
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#define compat_sp_abt regs[20]
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#define compat_lr_abt regs[21]
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#define compat_sp_und regs[22]
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#define compat_lr_und regs[23]
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#define compat_r8_fiq regs[24]
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#define compat_r9_fiq regs[25]
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#define compat_r10_fiq regs[26]
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#define compat_r11_fiq regs[27]
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#define compat_r12_fiq regs[28]
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#define compat_sp_fiq regs[29]
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#define compat_lr_fiq regs[30]
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/*
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* This struct defines the way the registers are stored on the stack during an
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* exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for
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* stack alignment). struct user_pt_regs must form a prefix of struct pt_regs.
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*/
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struct pt_regs {
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union {
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struct user_pt_regs user_regs;
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struct {
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u64 regs[31];
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u64 sp;
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u64 pc;
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u64 pstate;
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};
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};
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u64 orig_x0;
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u64 syscallno;
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};
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#define arch_has_single_step() (1)
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#ifdef CONFIG_COMPAT
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#define compat_thumb_mode(regs) \
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(((regs)->pstate & COMPAT_PSR_T_BIT))
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#else
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#define compat_thumb_mode(regs) (0)
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#endif
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#define user_mode(regs) \
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(((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t)
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#define compat_user_mode(regs) \
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(((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \
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(PSR_MODE32_BIT | PSR_MODE_EL0t))
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#define processor_mode(regs) \
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((regs)->pstate & PSR_MODE_MASK)
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#define interrupts_enabled(regs) \
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(!((regs)->pstate & PSR_I_BIT))
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#define fast_interrupts_enabled(regs) \
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(!((regs)->pstate & PSR_F_BIT))
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#define user_stack_pointer(regs) \
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(!compat_user_mode(regs) ? (regs)->sp : (regs)->compat_sp)
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static inline unsigned long regs_return_value(struct pt_regs *regs)
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{
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return regs->regs[0];
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}
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/*
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* Are the current registers suitable for user mode? (used to maintain
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* security in signal handlers)
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*/
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static inline int valid_user_regs(struct user_pt_regs *regs)
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{
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if (user_mode(regs) && (regs->pstate & PSR_I_BIT) == 0) {
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regs->pstate &= ~(PSR_F_BIT | PSR_A_BIT);
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/* The T bit is reserved for AArch64 */
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if (!(regs->pstate & PSR_MODE32_BIT))
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regs->pstate &= ~COMPAT_PSR_T_BIT;
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return 1;
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}
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/*
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* Force PSR to something logical...
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*/
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regs->pstate &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | \
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COMPAT_PSR_T_BIT | PSR_MODE32_BIT;
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if (!(regs->pstate & PSR_MODE32_BIT)) {
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regs->pstate &= ~COMPAT_PSR_T_BIT;
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regs->pstate |= PSR_MODE_EL0t;
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}
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return 0;
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}
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#define instruction_pointer(regs) ((unsigned long)(regs)->pc)
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#ifdef CONFIG_SMP
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extern unsigned long profile_pc(struct pt_regs *regs);
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#else
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#define profile_pc(regs) instruction_pointer(regs)
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#endif
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#endif /* __ASSEMBLY__ */
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#endif
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