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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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47f21315a6
Add a driver based meson clk-regmap to control clock phase on amlogic SoCs Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
64 lines
1.6 KiB
C
64 lines
1.6 KiB
C
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (c) 2018 BayLibre, SAS.
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* Author: Jerome Brunet <jbrunet@baylibre.com>
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*/
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#include <linux/clk-provider.h>
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#include "clkc.h"
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#define phase_step(_width) (360 / (1 << (_width)))
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static inline struct meson_clk_phase_data *
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meson_clk_phase_data(struct clk_regmap *clk)
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{
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return (struct meson_clk_phase_data *)clk->data;
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}
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int meson_clk_degrees_from_val(unsigned int val, unsigned int width)
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{
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return phase_step(width) * val;
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}
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EXPORT_SYMBOL_GPL(meson_clk_degrees_from_val);
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unsigned int meson_clk_degrees_to_val(int degrees, unsigned int width)
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{
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unsigned int val = DIV_ROUND_CLOSEST(degrees, phase_step(width));
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/*
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* This last calculation is here for cases when degrees is rounded
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* to 360, in which case val == (1 << width).
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*/
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return val % (1 << width);
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}
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EXPORT_SYMBOL_GPL(meson_clk_degrees_to_val);
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static int meson_clk_phase_get_phase(struct clk_hw *hw)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_clk_phase_data *phase = meson_clk_phase_data(clk);
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unsigned int val;
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val = meson_parm_read(clk->map, &phase->ph);
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return meson_clk_degrees_from_val(val, phase->ph.width);
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}
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static int meson_clk_phase_set_phase(struct clk_hw *hw, int degrees)
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{
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struct clk_regmap *clk = to_clk_regmap(hw);
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struct meson_clk_phase_data *phase = meson_clk_phase_data(clk);
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unsigned int val;
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val = meson_clk_degrees_to_val(degrees, phase->ph.width);
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meson_parm_write(clk->map, &phase->ph, val);
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return 0;
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}
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const struct clk_ops meson_clk_phase_ops = {
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.get_phase = meson_clk_phase_get_phase,
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.set_phase = meson_clk_phase_set_phase,
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};
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EXPORT_SYMBOL_GPL(meson_clk_phase_ops);
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