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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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2fa36399e6
Loongson 1B is a 32-bit SoC designed by Institute of Computing Technology (ICT) and the Chinese Academy of Sciences (CAS), which implements the MIPS32 release 2 instruction set. [ralf@linux-mips.org: But which is not strictly a MIPS32 compliant device which also is why it identifies itself with the Legacy Vendor ID in the PrID register. When applying the patch I shoveled some code around to keep things in alphabetical order and avoid forward declarations.] Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com> Cc: To: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: wuzhangjin@gmail.com Cc: zhzhl555@gmail.com Cc: Kelvin Cheung <keguang.zhang@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/3976/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
133 lines
2.9 KiB
C
133 lines
2.9 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2004, 2005 Ralf Baechle
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* Copyright (C) 2005 MIPS Technologies, Inc.
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*/
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#include <linux/compiler.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/oprofile.h>
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#include <linux/smp.h>
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#include <asm/cpu-info.h>
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#include "op_impl.h"
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extern struct op_mips_model op_model_mipsxx_ops __weak;
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extern struct op_mips_model op_model_rm9000_ops __weak;
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extern struct op_mips_model op_model_loongson2_ops __weak;
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static struct op_mips_model *model;
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static struct op_counter_config ctr[20];
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static int op_mips_setup(void)
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{
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/* Pre-compute the values to stuff in the hardware registers. */
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model->reg_setup(ctr);
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/* Configure the registers on all cpus. */
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on_each_cpu(model->cpu_setup, NULL, 1);
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return 0;
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}
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static int op_mips_create_files(struct super_block *sb, struct dentry *root)
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{
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int i;
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for (i = 0; i < model->num_counters; ++i) {
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struct dentry *dir;
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char buf[4];
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snprintf(buf, sizeof buf, "%d", i);
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dir = oprofilefs_mkdir(sb, root, buf);
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oprofilefs_create_ulong(sb, dir, "enabled", &ctr[i].enabled);
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oprofilefs_create_ulong(sb, dir, "event", &ctr[i].event);
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oprofilefs_create_ulong(sb, dir, "count", &ctr[i].count);
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oprofilefs_create_ulong(sb, dir, "kernel", &ctr[i].kernel);
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oprofilefs_create_ulong(sb, dir, "user", &ctr[i].user);
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oprofilefs_create_ulong(sb, dir, "exl", &ctr[i].exl);
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/* Dummy. */
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oprofilefs_create_ulong(sb, dir, "unit_mask", &ctr[i].unit_mask);
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}
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return 0;
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}
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static int op_mips_start(void)
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{
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on_each_cpu(model->cpu_start, NULL, 1);
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return 0;
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}
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static void op_mips_stop(void)
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{
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/* Disable performance monitoring for all counters. */
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on_each_cpu(model->cpu_stop, NULL, 1);
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}
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int __init oprofile_arch_init(struct oprofile_operations *ops)
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{
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struct op_mips_model *lmodel = NULL;
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int res;
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switch (current_cpu_type()) {
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case CPU_5KC:
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case CPU_M14KC:
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case CPU_20KC:
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case CPU_24K:
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case CPU_25KF:
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case CPU_34K:
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case CPU_1004K:
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case CPU_74K:
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case CPU_LOONGSON1:
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case CPU_SB1:
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case CPU_SB1A:
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case CPU_R10000:
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case CPU_R12000:
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case CPU_R14000:
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lmodel = &op_model_mipsxx_ops;
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break;
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case CPU_RM9000:
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lmodel = &op_model_rm9000_ops;
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break;
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case CPU_LOONGSON2:
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lmodel = &op_model_loongson2_ops;
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break;
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};
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if (!lmodel)
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return -ENODEV;
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res = lmodel->init();
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if (res)
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return res;
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model = lmodel;
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ops->create_files = op_mips_create_files;
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ops->setup = op_mips_setup;
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//ops->shutdown = op_mips_shutdown;
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ops->start = op_mips_start;
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ops->stop = op_mips_stop;
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ops->cpu_type = lmodel->cpu_type;
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ops->backtrace = op_mips_backtrace;
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printk(KERN_INFO "oprofile: using %s performance monitoring.\n",
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lmodel->cpu_type);
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return 0;
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}
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void oprofile_arch_exit(void)
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{
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if (model)
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model->exit();
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}
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