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11483b5c22
The whole code around eeprom is distributed across whole bunch of different files, most of which belong to the to-be-DVM code. As a result, it is currently very hard to split out the EEPROM code to be generic. However, it is also quite unlikely that the current EEPROM code will be needed by the MVM code as that has different mechanisms to query the EEPROM (it does so through the uCode.) So, at least temporarily, move everything into priv. If it becomes necessary to use the code from MVM, we will have to split it out, but then it's also easier since we'll know what pieces we need. Signed-off-by: Johannes Berg <johannes.berg@intel.com> Signed-off-by: Wey-Yi Guy <wey-yi.w.guy@intel.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
323 lines
12 KiB
C
323 lines
12 KiB
C
/******************************************************************************
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2008 - 2012 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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* USA
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*
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* The full GNU General Public License is included in this distribution
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* in the file called LICENSE.GPL.
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*
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* Contact Information:
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* Intel Linux Wireless <ilw@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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* BSD LICENSE
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*
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* Copyright(c) 2005 - 2012 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*****************************************************************************/
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#ifndef __iwl_eeprom_h__
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#define __iwl_eeprom_h__
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#include <net/mac80211.h>
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struct iwl_priv;
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/*
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* EEPROM access time values:
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*
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* Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG.
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* Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1).
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* When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec.
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* Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
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*/
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#define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */
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#define IWL_EEPROM_SEM_TIMEOUT 10 /* microseconds */
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#define IWL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */
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/*
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* Regulatory channel usage flags in EEPROM struct iwl4965_eeprom_channel.flags.
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*
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* IBSS and/or AP operation is allowed *only* on those channels with
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* (VALID && IBSS && ACTIVE && !RADAR). This restriction is in place because
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* RADAR detection is not supported by the 4965 driver, but is a
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* requirement for establishing a new network for legal operation on channels
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* requiring RADAR detection or restricting ACTIVE scanning.
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*
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* NOTE: "WIDE" flag does not indicate anything about "HT40" 40 MHz channels.
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* It only indicates that 20 MHz channel use is supported; HT40 channel
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* usage is indicated by a separate set of regulatory flags for each
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* HT40 channel pair.
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*
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* NOTE: Using a channel inappropriately will result in a uCode error!
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*/
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#define IWL_NUM_TX_CALIB_GROUPS 5
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enum {
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EEPROM_CHANNEL_VALID = (1 << 0), /* usable for this SKU/geo */
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EEPROM_CHANNEL_IBSS = (1 << 1), /* usable as an IBSS channel */
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/* Bit 2 Reserved */
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EEPROM_CHANNEL_ACTIVE = (1 << 3), /* active scanning allowed */
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EEPROM_CHANNEL_RADAR = (1 << 4), /* radar detection required */
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EEPROM_CHANNEL_WIDE = (1 << 5), /* 20 MHz channel okay */
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/* Bit 6 Reserved (was Narrow Channel) */
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EEPROM_CHANNEL_DFS = (1 << 7), /* dynamic freq selection candidate */
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};
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/* SKU Capabilities */
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#define EEPROM_SKU_CAP_BAND_24GHZ (1 << 4)
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#define EEPROM_SKU_CAP_BAND_52GHZ (1 << 5)
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#define EEPROM_SKU_CAP_11N_ENABLE (1 << 6)
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#define EEPROM_SKU_CAP_AMT_ENABLE (1 << 7)
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#define EEPROM_SKU_CAP_IPAN_ENABLE (1 << 8)
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/* *regulatory* channel data format in eeprom, one for each channel.
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* There are separate entries for HT40 (40 MHz) vs. normal (20 MHz) channels. */
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struct iwl_eeprom_channel {
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u8 flags; /* EEPROM_CHANNEL_* flags copied from EEPROM */
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s8 max_power_avg; /* max power (dBm) on this chnl, limit 31 */
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} __packed;
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enum iwl_eeprom_enhanced_txpwr_flags {
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IWL_EEPROM_ENH_TXP_FL_VALID = BIT(0),
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IWL_EEPROM_ENH_TXP_FL_BAND_52G = BIT(1),
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IWL_EEPROM_ENH_TXP_FL_OFDM = BIT(2),
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IWL_EEPROM_ENH_TXP_FL_40MHZ = BIT(3),
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IWL_EEPROM_ENH_TXP_FL_HT_AP = BIT(4),
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IWL_EEPROM_ENH_TXP_FL_RES1 = BIT(5),
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IWL_EEPROM_ENH_TXP_FL_RES2 = BIT(6),
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IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE = BIT(7),
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};
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/**
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* iwl_eeprom_enhanced_txpwr structure
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* This structure presents the enhanced regulatory tx power limit layout
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* in eeprom image
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* Enhanced regulatory tx power portion of eeprom image can be broken down
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* into individual structures; each one is 8 bytes in size and contain the
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* following information
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* @flags: entry flags
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* @channel: channel number
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* @chain_a_max_pwr: chain a max power in 1/2 dBm
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* @chain_b_max_pwr: chain b max power in 1/2 dBm
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* @chain_c_max_pwr: chain c max power in 1/2 dBm
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* @delta_20_in_40: 20-in-40 deltas (hi/lo)
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* @mimo2_max_pwr: mimo2 max power in 1/2 dBm
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* @mimo3_max_pwr: mimo3 max power in 1/2 dBm
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*
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*/
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struct iwl_eeprom_enhanced_txpwr {
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u8 flags;
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u8 channel;
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s8 chain_a_max;
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s8 chain_b_max;
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s8 chain_c_max;
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u8 delta_20_in_40;
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s8 mimo2_max;
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s8 mimo3_max;
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} __packed;
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/* calibration */
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struct iwl_eeprom_calib_hdr {
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u8 version;
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u8 pa_type;
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__le16 voltage;
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} __packed;
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#define EEPROM_CALIB_ALL (INDIRECT_ADDRESS | INDIRECT_CALIBRATION)
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#define EEPROM_XTAL ((2*0x128) | EEPROM_CALIB_ALL)
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/* temperature */
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#define EEPROM_KELVIN_TEMPERATURE ((2*0x12A) | EEPROM_CALIB_ALL)
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#define EEPROM_RAW_TEMPERATURE ((2*0x12B) | EEPROM_CALIB_ALL)
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/* agn links */
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#define EEPROM_LINK_HOST (2*0x64)
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#define EEPROM_LINK_GENERAL (2*0x65)
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#define EEPROM_LINK_REGULATORY (2*0x66)
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#define EEPROM_LINK_CALIBRATION (2*0x67)
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#define EEPROM_LINK_PROCESS_ADJST (2*0x68)
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#define EEPROM_LINK_OTHERS (2*0x69)
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#define EEPROM_LINK_TXP_LIMIT (2*0x6a)
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#define EEPROM_LINK_TXP_LIMIT_SIZE (2*0x6b)
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/* agn regulatory - indirect access */
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#define EEPROM_REG_BAND_1_CHANNELS ((0x08)\
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| INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 28 bytes */
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#define EEPROM_REG_BAND_2_CHANNELS ((0x26)\
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| INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 26 bytes */
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#define EEPROM_REG_BAND_3_CHANNELS ((0x42)\
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| INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 24 bytes */
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#define EEPROM_REG_BAND_4_CHANNELS ((0x5C)\
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| INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 22 bytes */
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#define EEPROM_REG_BAND_5_CHANNELS ((0x74)\
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| INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 12 bytes */
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#define EEPROM_REG_BAND_24_HT40_CHANNELS ((0x82)\
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| INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 14 bytes */
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#define EEPROM_REG_BAND_52_HT40_CHANNELS ((0x92)\
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| INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 22 bytes */
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/* 6000 regulatory - indirect access */
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#define EEPROM_6000_REG_BAND_24_HT40_CHANNELS ((0x80)\
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| INDIRECT_ADDRESS | INDIRECT_REGULATORY) /* 14 bytes */
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/* 5000 Specific */
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#define EEPROM_5000_TX_POWER_VERSION (4)
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#define EEPROM_5000_EEPROM_VERSION (0x11A)
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/* 5050 Specific */
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#define EEPROM_5050_TX_POWER_VERSION (4)
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#define EEPROM_5050_EEPROM_VERSION (0x21E)
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/* 1000 Specific */
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#define EEPROM_1000_TX_POWER_VERSION (4)
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#define EEPROM_1000_EEPROM_VERSION (0x15C)
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/* 6x00 Specific */
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#define EEPROM_6000_TX_POWER_VERSION (4)
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#define EEPROM_6000_EEPROM_VERSION (0x423)
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/* 6x50 Specific */
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#define EEPROM_6050_TX_POWER_VERSION (4)
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#define EEPROM_6050_EEPROM_VERSION (0x532)
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/* 6150 Specific */
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#define EEPROM_6150_TX_POWER_VERSION (6)
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#define EEPROM_6150_EEPROM_VERSION (0x553)
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/* 6x05 Specific */
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#define EEPROM_6005_TX_POWER_VERSION (6)
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#define EEPROM_6005_EEPROM_VERSION (0x709)
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/* 6x30 Specific */
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#define EEPROM_6030_TX_POWER_VERSION (6)
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#define EEPROM_6030_EEPROM_VERSION (0x709)
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/* 2x00 Specific */
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#define EEPROM_2000_TX_POWER_VERSION (6)
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#define EEPROM_2000_EEPROM_VERSION (0x805)
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/* 6x35 Specific */
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#define EEPROM_6035_TX_POWER_VERSION (6)
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#define EEPROM_6035_EEPROM_VERSION (0x753)
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/* OTP */
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/* lower blocks contain EEPROM image and calibration data */
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#define OTP_LOW_IMAGE_SIZE (2 * 512 * sizeof(u16)) /* 2 KB */
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/* high blocks contain PAPD data */
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#define OTP_HIGH_IMAGE_SIZE_6x00 (6 * 512 * sizeof(u16)) /* 6 KB */
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#define OTP_HIGH_IMAGE_SIZE_1000 (0x200 * sizeof(u16)) /* 1024 bytes */
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#define OTP_MAX_LL_ITEMS_1000 (3) /* OTP blocks for 1000 */
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#define OTP_MAX_LL_ITEMS_6x00 (4) /* OTP blocks for 6x00 */
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#define OTP_MAX_LL_ITEMS_6x50 (7) /* OTP blocks for 6x50 */
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#define OTP_MAX_LL_ITEMS_2x00 (4) /* OTP blocks for 2x00 */
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/* 2.4 GHz */
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extern const u8 iwl_eeprom_band_1[14];
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#define ADDRESS_MSK 0x0000FFFF
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#define INDIRECT_TYPE_MSK 0x000F0000
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#define INDIRECT_HOST 0x00010000
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#define INDIRECT_GENERAL 0x00020000
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#define INDIRECT_REGULATORY 0x00030000
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#define INDIRECT_CALIBRATION 0x00040000
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#define INDIRECT_PROCESS_ADJST 0x00050000
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#define INDIRECT_OTHERS 0x00060000
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#define INDIRECT_TXP_LIMIT 0x00070000
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#define INDIRECT_TXP_LIMIT_SIZE 0x00080000
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#define INDIRECT_ADDRESS 0x00100000
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/* General */
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#define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */
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#define EEPROM_SUBSYSTEM_ID (2*0x0A) /* 2 bytes */
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#define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */
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#define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */
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#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */
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#define EEPROM_VERSION (2*0x44) /* 2 bytes */
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#define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */
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#define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */
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#define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */
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#define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */
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/* The following masks are to be applied on EEPROM_RADIO_CONFIG */
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#define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */
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#define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */
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#define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */
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#define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */
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#define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */
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#define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */
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#define EEPROM_RF_CONFIG_TYPE_MAX 0x3
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#define EEPROM_REGULATORY_BAND_NO_HT40 (0)
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struct iwl_eeprom_ops {
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const u32 regulatory_bands[7];
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bool enhanced_txpower;
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};
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int iwl_eeprom_init(struct iwl_priv *priv, u32 hw_rev);
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void iwl_eeprom_free(struct iwl_priv *priv);
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int iwl_eeprom_check_version(struct iwl_priv *priv);
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int iwl_eeprom_init_hw_params(struct iwl_priv *priv);
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u16 iwl_eeprom_calib_version(struct iwl_priv *priv);
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const u8 *iwl_eeprom_query_addr(struct iwl_priv *priv, size_t offset);
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u16 iwl_eeprom_query16(struct iwl_priv *priv, size_t offset);
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void iwl_eeprom_get_mac(struct iwl_priv *priv, u8 *mac);
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int iwl_init_channel_map(struct iwl_priv *priv);
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void iwl_free_channel_map(struct iwl_priv *priv);
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const struct iwl_channel_info *iwl_get_channel_info(
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const struct iwl_priv *priv,
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enum ieee80211_band band, u16 channel);
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void iwl_rf_config(struct iwl_priv *priv);
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#endif /* __iwl_eeprom_h__ */
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