mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-19 06:36:44 +07:00
e9f5f1e456
All the boards booting with device tree use drivers/pinctrl-single.c instead. Note that mach-omap1 is still using the legacy mux, so let's move the related Kconfig options from plat-omap to mach-omap1. Signed-off-by: Tony Lindgren <tony@atomide.com>
90 lines
2.6 KiB
C
90 lines
2.6 KiB
C
/*
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* MSDI IP block reset
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*
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* Copyright (C) 2012 Texas Instruments, Inc.
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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* XXX What about pad muxing?
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/platform_data/gpio-omap.h>
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#include "prm.h"
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#include "common.h"
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#include "control.h"
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#include "omap_hwmod.h"
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#include "omap_device.h"
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#include "mmc.h"
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/*
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* MSDI_CON_OFFSET: offset in bytes of the MSDI IP block's CON register
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* from the IP block's base address
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*/
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#define MSDI_CON_OFFSET 0x0c
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/* Register bitfields in the CON register */
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#define MSDI_CON_POW_MASK BIT(11)
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#define MSDI_CON_CLKD_MASK (0x3f << 0)
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#define MSDI_CON_CLKD_SHIFT 0
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/* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */
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#define MSDI_TARGET_RESET_CLKD 0x3ff
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/**
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* omap_msdi_reset - reset the MSDI IP block
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* @oh: struct omap_hwmod *
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*
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* The MSDI IP block on OMAP2420 has to have both the POW and CLKD
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* fields set inside its CON register for a reset to complete
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* successfully. This is not documented in the TRM. For CLKD, we use
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* the value that results in the lowest possible clock rate, to attempt
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* to avoid disturbing any cards.
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*/
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int omap_msdi_reset(struct omap_hwmod *oh)
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{
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u16 v = 0;
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int c = 0;
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/* Write to the SOFTRESET bit */
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omap_hwmod_softreset(oh);
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/* Enable the MSDI core and internal clock */
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v |= MSDI_CON_POW_MASK;
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v |= MSDI_TARGET_RESET_CLKD << MSDI_CON_CLKD_SHIFT;
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omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
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/* Poll on RESETDONE bit */
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omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
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& SYSS_RESETDONE_MASK),
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MAX_MODULE_SOFTRESET_WAIT, c);
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if (c == MAX_MODULE_SOFTRESET_WAIT)
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pr_warn("%s: %s: softreset failed (waited %d usec)\n",
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__func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
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else
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pr_debug("%s: %s: softreset in %d usec\n", __func__,
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oh->name, c);
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/* Disable the MSDI internal clock */
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v &= ~MSDI_CON_CLKD_MASK;
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omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
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return 0;
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}
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