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This commit extends the existing clk-cpu driver used on Marvell Armada XP platforms to support the dynamic frequency scaling of the CPU clock. Non-dynamic frequency change was already supported (and used before secondary CPUs are started), but the dynamic frequency change requires a completely different procedure. In order to achieve this, the clk_cpu_set_rate() function is reworked to handle two separate cases: - The case where the clock is enabled, which is the new dynamic frequency change code, implemented in clk_cpu_on_set_rate(). This part will be used for cpufreq activities. - The case where the clock is disabled, which is the existing frequency change code, moved in clk_cpu_off_set_rate(). This part is already used to set the clock frequency of the secondary CPUs before starting them. In order to implement the dynamic frequency change function, we need to access the PMU DFS registers, which are outside the currently mapped "Clock Complex" registers, so a new area of registers is now mapped. This affects the Device Tree binding, but we are careful to do it in a backward-compatible way (by allowing the second pair of registers to be non-existent, and in this case, ensuring clk_cpu_on_set_rate() returns an error). Note that technically speaking, the clk_cpu_on_set_rate() does not do the entire procedure needed to change the frequency dynamically, as it involves touching a number of PMSU registers. This is done through a clock notifier registered by the PMSU driver in followup commits. Cc: <devicetree@vger.kernel.org> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1404920715-19834-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
23 lines
671 B
Plaintext
23 lines
671 B
Plaintext
Device Tree Clock bindings for cpu clock of Marvell EBU platforms
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Required properties:
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- compatible : shall be one of the following:
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"marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
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- reg : Address and length of the clock complex register set, followed
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by address and length of the PMU DFS registers
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- #clock-cells : should be set to 1.
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- clocks : shall be the input parent clock phandle for the clock.
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cpuclk: clock-complex@d0018700 {
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#clock-cells = <1>;
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compatible = "marvell,armada-xp-cpu-clock";
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reg = <0xd0018700 0xA0>, <0x1c054 0x10>;
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clocks = <&coreclk 1>;
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}
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cpu@0 {
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compatible = "marvell,sheeva-v7";
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reg = <0>;
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clocks = <&cpuclk 0>;
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};
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