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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1887c3a64f
This patch adds support for the new v2 version of the axi-clkgen core. Unfortunately the method of accessing the registers is quite different on v2, while the content still stays largely the same. So the patch adds a small abstraction layer which implements the specific read and write functions for v1 and v2 in callback functions. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
23 lines
655 B
Plaintext
23 lines
655 B
Plaintext
Binding for the axi-clkgen clock generator
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This binding uses the common clock binding[1].
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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Required properties:
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- compatible : shall be "adi,axi-clkgen-1.00.a" or "adi,axi-clkgen-2.00.a".
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- #clock-cells : from common clock binding; Should always be set to 0.
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- reg : Address and length of the axi-clkgen register set.
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- clocks : Phandle and clock specifier for the parent clock.
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Optional properties:
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- clock-output-names : From common clock binding.
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Example:
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clock@0xff000000 {
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compatible = "adi,axi-clkgen";
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#clock-cells = <0>;
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reg = <0xff000000 0x1000>;
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clocks = <&osc 1>;
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};
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