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d4cea38ebb
After the commit mentioned below, we start computing the byte and pixel
clocks (dsi_calc_clk_rate) in the DSI bridge's mode_set() op. The
calculation involves the number of DSI lanes being used by the
downstream bridge/panel.
If the downstream bridge/panel tries to change the number of DSI lanes
(as done in the ADV7533 driver) in its mode_set() op, then our DSI
host driver will not have the correct number of lanes when computing
byte/pixel clocks.
Fix this by delaying the clock rate calculation in the DSI bridge
enable path. In particular, compute the clock rates in
msm_dsi_host_get_phy_clk_req().
This fixes the DSI host error interrupts seen when we try to switch
between modes that require different number of lanes (4 to 3 lanes, or
vice versa) on db410c. The error interrupts occur since the byte/pixel
clock rates aren't according to what the DSI video mode timing engine
expects.
Fixes:
|
||
|---|---|---|
| .. | ||
| phy | ||
| pll | ||
| dsi_cfg.c | ||
| dsi_cfg.h | ||
| dsi_host.c | ||
| dsi_manager.c | ||
| dsi.c | ||
| dsi.h | ||
| dsi.xml.h | ||
| mmss_cc.xml.h | ||
| sfpb.xml.h | ||