Valentin Longchamp 2ccf80b756 soc/fsl/qe: round brg_freq to 1kHz granularity ... Because of integer computation rounding in u-boot (that sets the QE brg-frequency DTS prop), the clk value is 99999999 Hz even though it is 100 MHz. When setting brg clks that are exact divisors of 100 MHz, this small differnce plays a role and can result in lower clks to be output (for instance 20 MHz - divide by 5 - results in 16.666 MHz - divide by 6). This patch fixes that by "forcing" the brg_clk to the nearest kHz when the difference is below 2 integer rounding errors (i.e. 4). Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Scott Wood <oss@buserror.net>		2017-04-30 01:31:51 -05:00
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bcm
dove	soc: dove: constify reset_control_ops structures	2017-01-27 17:52:57 +01:00
fsl	soc/fsl/qe: round brg_freq to 1kHz granularity	2017-04-30 01:31:51 -05:00
mediatek
qcom	remoteproc: qcom: mdt_loader: Use signed type for offset	2017-02-22 02:07:13 -08:00
renesas
rockchip	soc: rockchip: add driver handling grf setup	2017-01-06 10:28:19 +01:00
samsung	Improve the PM domains driver for Exynos by displaying a user-friendly name of	2017-02-07 17:20:07 +01:00
sunxi
tegra
ti	ARM: SoC driver updates	2017-02-23 15:57:04 -08:00
ux500
versatile
zte	soc: zte: pm_domains: Add support for zx296718	2017-01-11 16:21:14 +08:00
Kconfig	soc: zte: pm_domains: Prepare for supporting ARMv8 zx2967 family	2017-01-11 16:21:10 +08:00
Makefile	soc: zte: pm_domains: Prepare for supporting ARMv8 zx2967 family	2017-01-11 16:21:10 +08:00