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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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297 lines
8.1 KiB
C
297 lines
8.1 KiB
C
/*
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* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
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* Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org)
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* Copyright (C) 2000 SiByte, Inc.
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* Copyright (C) 2005 Thiemo Seufer
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*
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* Written by Justin Carlson of SiByte, Inc.
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* and Kip Walker of Broadcom Corp.
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*
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <asm/io.h>
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#include <asm/sibyte/sb1250.h>
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#include <asm/sibyte/sb1250_regs.h>
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#include <asm/sibyte/sb1250_dma.h>
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#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
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#define SB1_PREF_LOAD_STREAMED_HINT "0"
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#define SB1_PREF_STORE_STREAMED_HINT "1"
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#else
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#define SB1_PREF_LOAD_STREAMED_HINT "4"
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#define SB1_PREF_STORE_STREAMED_HINT "5"
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#endif
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static inline void clear_page_cpu(void *page)
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{
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unsigned char *addr = (unsigned char *) page;
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unsigned char *end = addr + PAGE_SIZE;
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/*
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* JDCXXX - This should be bottlenecked by the write buffer, but these
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* things tend to be mildly unpredictable...should check this on the
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* performance model
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*
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* We prefetch 4 lines ahead. We're also "cheating" slightly here...
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* since we know we're on an SB1, we force the assembler to take
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* 64-bit operands to speed things up
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*/
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__asm__ __volatile__(
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" .set push \n"
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" .set mips4 \n"
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" .set noreorder \n"
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#ifdef CONFIG_CPU_HAS_PREFETCH
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" daddiu %0, %0, 128 \n"
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" pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%0) \n"
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/* Prefetch the first 4 lines */
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" pref " SB1_PREF_STORE_STREAMED_HINT ", -96(%0) \n"
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" pref " SB1_PREF_STORE_STREAMED_HINT ", -64(%0) \n"
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" pref " SB1_PREF_STORE_STREAMED_HINT ", -32(%0) \n"
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"1: sd $0, -128(%0) \n" /* Throw out a cacheline of 0's */
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" sd $0, -120(%0) \n"
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" sd $0, -112(%0) \n"
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" sd $0, -104(%0) \n"
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" daddiu %0, %0, 32 \n"
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" bnel %0, %1, 1b \n"
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" pref " SB1_PREF_STORE_STREAMED_HINT ", -32(%0) \n"
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" daddiu %0, %0, -128 \n"
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#endif
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" sd $0, 0(%0) \n" /* Throw out a cacheline of 0's */
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"1: sd $0, 8(%0) \n"
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" sd $0, 16(%0) \n"
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" sd $0, 24(%0) \n"
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" daddiu %0, %0, 32 \n"
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" bnel %0, %1, 1b \n"
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" sd $0, 0(%0) \n"
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" .set pop \n"
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: "+r" (addr)
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: "r" (end)
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: "memory");
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}
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static inline void copy_page_cpu(void *to, void *from)
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{
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unsigned char *src = (unsigned char *)from;
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unsigned char *dst = (unsigned char *)to;
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unsigned char *end = src + PAGE_SIZE;
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/*
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* The pref's used here are using "streaming" hints, which cause the
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* copied data to be kicked out of the cache sooner. A page copy often
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* ends up copying a lot more data than is commonly used, so this seems
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* to make sense in terms of reducing cache pollution, but I've no real
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* performance data to back this up
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*/
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__asm__ __volatile__(
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" .set push \n"
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" .set mips4 \n"
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" .set noreorder \n"
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#ifdef CONFIG_CPU_HAS_PREFETCH
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" daddiu %0, %0, 128 \n"
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" daddiu %1, %1, 128 \n"
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" pref " SB1_PREF_LOAD_STREAMED_HINT ", -128(%0)\n"
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/* Prefetch the first 4 lines */
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" pref " SB1_PREF_STORE_STREAMED_HINT ", -128(%1)\n"
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" pref " SB1_PREF_LOAD_STREAMED_HINT ", -96(%0)\n"
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" pref " SB1_PREF_STORE_STREAMED_HINT ", -96(%1)\n"
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" pref " SB1_PREF_LOAD_STREAMED_HINT ", -64(%0)\n"
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" pref " SB1_PREF_STORE_STREAMED_HINT ", -64(%1)\n"
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" pref " SB1_PREF_LOAD_STREAMED_HINT ", -32(%0)\n"
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"1: pref " SB1_PREF_STORE_STREAMED_HINT ", -32(%1)\n"
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# ifdef CONFIG_64BIT
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" ld $8, -128(%0) \n" /* Block copy a cacheline */
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" ld $9, -120(%0) \n"
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" ld $10, -112(%0) \n"
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" ld $11, -104(%0) \n"
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" sd $8, -128(%1) \n"
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" sd $9, -120(%1) \n"
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" sd $10, -112(%1) \n"
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" sd $11, -104(%1) \n"
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# else
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" lw $2, -128(%0) \n" /* Block copy a cacheline */
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" lw $3, -124(%0) \n"
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" lw $6, -120(%0) \n"
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" lw $7, -116(%0) \n"
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" lw $8, -112(%0) \n"
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" lw $9, -108(%0) \n"
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" lw $10, -104(%0) \n"
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" lw $11, -100(%0) \n"
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" sw $2, -128(%1) \n"
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" sw $3, -124(%1) \n"
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" sw $6, -120(%1) \n"
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" sw $7, -116(%1) \n"
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" sw $8, -112(%1) \n"
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" sw $9, -108(%1) \n"
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" sw $10, -104(%1) \n"
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" sw $11, -100(%1) \n"
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# endif
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" daddiu %0, %0, 32 \n"
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" daddiu %1, %1, 32 \n"
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" bnel %0, %2, 1b \n"
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" pref " SB1_PREF_LOAD_STREAMED_HINT ", -32(%0)\n"
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" daddiu %0, %0, -128 \n"
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" daddiu %1, %1, -128 \n"
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#endif
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#ifdef CONFIG_64BIT
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" ld $8, 0(%0) \n" /* Block copy a cacheline */
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"1: ld $9, 8(%0) \n"
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" ld $10, 16(%0) \n"
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" ld $11, 24(%0) \n"
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" sd $8, 0(%1) \n"
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" sd $9, 8(%1) \n"
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" sd $10, 16(%1) \n"
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" sd $11, 24(%1) \n"
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#else
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" lw $2, 0(%0) \n" /* Block copy a cacheline */
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"1: lw $3, 4(%0) \n"
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" lw $6, 8(%0) \n"
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" lw $7, 12(%0) \n"
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" lw $8, 16(%0) \n"
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" lw $9, 20(%0) \n"
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" lw $10, 24(%0) \n"
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" lw $11, 28(%0) \n"
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" sw $2, 0(%1) \n"
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" sw $3, 4(%1) \n"
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" sw $6, 8(%1) \n"
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" sw $7, 12(%1) \n"
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" sw $8, 16(%1) \n"
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" sw $9, 20(%1) \n"
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" sw $10, 24(%1) \n"
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" sw $11, 28(%1) \n"
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#endif
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" daddiu %0, %0, 32 \n"
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" daddiu %1, %1, 32 \n"
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" bnel %0, %2, 1b \n"
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#ifdef CONFIG_64BIT
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" ld $8, 0(%0) \n"
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#else
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" lw $2, 0(%0) \n"
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#endif
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" .set pop \n"
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: "+r" (src), "+r" (dst)
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: "r" (end)
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#ifdef CONFIG_64BIT
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: "$8","$9","$10","$11","memory");
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#else
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: "$2","$3","$6","$7","$8","$9","$10","$11","memory");
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#endif
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}
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#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
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/*
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* Pad descriptors to cacheline, since each is exclusively owned by a
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* particular CPU.
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*/
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typedef struct dmadscr_s {
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u64 dscr_a;
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u64 dscr_b;
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u64 pad_a;
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u64 pad_b;
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} dmadscr_t;
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static dmadscr_t page_descr[DM_NUM_CHANNELS]
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__attribute__((aligned(SMP_CACHE_BYTES)));
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void sb1_dma_init(void)
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{
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int i;
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for (i = 0; i < DM_NUM_CHANNELS; i++) {
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const u64 base_val = CPHYSADDR(&page_descr[i]) |
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V_DM_DSCR_BASE_RINGSZ(1);
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volatile void *base_reg =
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IOADDR(A_DM_REGISTER(i, R_DM_DSCR_BASE));
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__raw_writeq(base_val, base_reg);
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__raw_writeq(base_val | M_DM_DSCR_BASE_RESET, base_reg);
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__raw_writeq(base_val | M_DM_DSCR_BASE_ENABL, base_reg);
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}
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}
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void clear_page(void *page)
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{
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u64 to_phys = CPHYSADDR(page);
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unsigned int cpu = smp_processor_id();
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/* if the page is not in KSEG0, use old way */
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if ((long)KSEGX(page) != (long)CKSEG0)
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return clear_page_cpu(page);
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page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_ZERO_MEM |
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M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT;
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page_descr[cpu].dscr_b = V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE);
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__raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
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/*
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* Don't really want to do it this way, but there's no
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* reliable way to delay completion detection.
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*/
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while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)))
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& M_DM_DSCR_BASE_INTERRUPT))
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;
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__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
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}
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void copy_page(void *to, void *from)
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{
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u64 from_phys = CPHYSADDR(from);
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u64 to_phys = CPHYSADDR(to);
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unsigned int cpu = smp_processor_id();
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/* if any page is not in KSEG0, use old way */
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if ((long)KSEGX(to) != (long)CKSEG0
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|| (long)KSEGX(from) != (long)CKSEG0)
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return copy_page_cpu(to, from);
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page_descr[cpu].dscr_a = to_phys | M_DM_DSCRA_L2C_DEST |
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M_DM_DSCRA_INTERRUPT;
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page_descr[cpu].dscr_b = from_phys | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE);
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__raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
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/*
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* Don't really want to do it this way, but there's no
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* reliable way to delay completion detection.
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*/
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while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)))
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& M_DM_DSCR_BASE_INTERRUPT))
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;
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__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
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}
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#else /* !CONFIG_SIBYTE_DMA_PAGEOPS */
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void clear_page(void *page)
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{
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return clear_page_cpu(page);
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}
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void copy_page(void *to, void *from)
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{
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return copy_page_cpu(to, from);
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}
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#endif /* !CONFIG_SIBYTE_DMA_PAGEOPS */
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EXPORT_SYMBOL(clear_page);
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EXPORT_SYMBOL(copy_page);
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