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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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02c68a0201
The workaround for AMD erratum 400 uses the term "c1e" falsely suggesting: 1. Intel C1E is somehow involved 2. All AMD processors with C1E are involved Use the string "amd_c1e" instead of simply "c1e" to clarify that this workaround is specific to AMD's version of C1E. Use the string "e400" to clarify that the workaround is specific to AMD processors with Erratum 400. This patch is text-substitution only, with no functional change. cc: x86@kernel.org Acked-by: Borislav Petkov <borislav.petkov@amd.com> Signed-off-by: Len Brown <len.brown@intel.com>
1147 lines
29 KiB
C
1147 lines
29 KiB
C
/*
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* processor_idle - idle state submodule to the ACPI processor driver
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*
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* Copyright (C) 2001, 2002 Andy Grover <andrew.grover@intel.com>
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* Copyright (C) 2001, 2002 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
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* Copyright (C) 2004, 2005 Dominik Brodowski <linux@brodo.de>
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* Copyright (C) 2004 Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
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* - Added processor hotplug support
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* Copyright (C) 2005 Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
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* - Added support for C3 on SMP
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or (at
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* your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/cpufreq.h>
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#include <linux/slab.h>
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#include <linux/acpi.h>
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#include <linux/dmi.h>
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#include <linux/moduleparam.h>
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#include <linux/sched.h> /* need_resched() */
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#include <linux/pm_qos_params.h>
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#include <linux/clockchips.h>
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#include <linux/cpuidle.h>
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#include <linux/irqflags.h>
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/*
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* Include the apic definitions for x86 to have the APIC timer related defines
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* available also for UP (on SMP it gets magically included via linux/smp.h).
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* asm/acpi.h is not an option, as it would require more include magic. Also
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* creating an empty asm-ia64/apic.h would just trade pest vs. cholera.
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*/
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#ifdef CONFIG_X86
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#include <asm/apic.h>
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#endif
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <acpi/acpi_bus.h>
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#include <acpi/processor.h>
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#include <asm/processor.h>
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#define PREFIX "ACPI: "
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#define ACPI_PROCESSOR_CLASS "processor"
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#define _COMPONENT ACPI_PROCESSOR_COMPONENT
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ACPI_MODULE_NAME("processor_idle");
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#define PM_TIMER_TICK_NS (1000000000ULL/PM_TIMER_FREQUENCY)
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#define C2_OVERHEAD 1 /* 1us */
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#define C3_OVERHEAD 1 /* 1us */
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#define PM_TIMER_TICKS_TO_US(p) (((p) * 1000)/(PM_TIMER_FREQUENCY/1000))
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static unsigned int max_cstate __read_mostly = ACPI_PROCESSOR_MAX_POWER;
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module_param(max_cstate, uint, 0000);
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static unsigned int nocst __read_mostly;
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module_param(nocst, uint, 0000);
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static int bm_check_disable __read_mostly;
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module_param(bm_check_disable, uint, 0000);
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static unsigned int latency_factor __read_mostly = 2;
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module_param(latency_factor, uint, 0644);
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static int disabled_by_idle_boot_param(void)
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{
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return boot_option_idle_override == IDLE_POLL ||
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boot_option_idle_override == IDLE_FORCE_MWAIT ||
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boot_option_idle_override == IDLE_HALT;
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}
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/*
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* IBM ThinkPad R40e crashes mysteriously when going into C2 or C3.
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* For now disable this. Probably a bug somewhere else.
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*
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* To skip this limit, boot/load with a large max_cstate limit.
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*/
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static int set_max_cstate(const struct dmi_system_id *id)
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{
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if (max_cstate > ACPI_PROCESSOR_MAX_POWER)
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return 0;
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printk(KERN_NOTICE PREFIX "%s detected - limiting to C%ld max_cstate."
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" Override with \"processor.max_cstate=%d\"\n", id->ident,
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(long)id->driver_data, ACPI_PROCESSOR_MAX_POWER + 1);
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max_cstate = (long)id->driver_data;
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return 0;
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}
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/* Actually this shouldn't be __cpuinitdata, would be better to fix the
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callers to only run once -AK */
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static struct dmi_system_id __cpuinitdata processor_power_dmi_table[] = {
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{ set_max_cstate, "Clevo 5600D", {
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DMI_MATCH(DMI_BIOS_VENDOR,"Phoenix Technologies LTD"),
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DMI_MATCH(DMI_BIOS_VERSION,"SHE845M0.86C.0013.D.0302131307")},
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(void *)2},
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{ set_max_cstate, "Pavilion zv5000", {
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DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
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DMI_MATCH(DMI_PRODUCT_NAME,"Pavilion zv5000 (DS502A#ABA)")},
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(void *)1},
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{ set_max_cstate, "Asus L8400B", {
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DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer Inc."),
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DMI_MATCH(DMI_PRODUCT_NAME,"L8400B series Notebook PC")},
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(void *)1},
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{},
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};
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/*
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* Callers should disable interrupts before the call and enable
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* interrupts after return.
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*/
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static void acpi_safe_halt(void)
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{
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current_thread_info()->status &= ~TS_POLLING;
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/*
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* TS_POLLING-cleared state must be visible before we
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* test NEED_RESCHED:
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*/
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smp_mb();
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if (!need_resched()) {
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safe_halt();
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local_irq_disable();
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}
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current_thread_info()->status |= TS_POLLING;
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}
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#ifdef ARCH_APICTIMER_STOPS_ON_C3
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/*
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* Some BIOS implementations switch to C3 in the published C2 state.
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* This seems to be a common problem on AMD boxen, but other vendors
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* are affected too. We pick the most conservative approach: we assume
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* that the local APIC stops in both C2 and C3.
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*/
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static void lapic_timer_check_state(int state, struct acpi_processor *pr,
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struct acpi_processor_cx *cx)
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{
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struct acpi_processor_power *pwr = &pr->power;
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u8 type = local_apic_timer_c2_ok ? ACPI_STATE_C3 : ACPI_STATE_C2;
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if (cpu_has(&cpu_data(pr->id), X86_FEATURE_ARAT))
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return;
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if (amd_e400_c1e_detected)
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type = ACPI_STATE_C1;
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/*
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* Check, if one of the previous states already marked the lapic
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* unstable
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*/
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if (pwr->timer_broadcast_on_state < state)
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return;
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if (cx->type >= type)
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pr->power.timer_broadcast_on_state = state;
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}
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static void __lapic_timer_propagate_broadcast(void *arg)
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{
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struct acpi_processor *pr = (struct acpi_processor *) arg;
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unsigned long reason;
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reason = pr->power.timer_broadcast_on_state < INT_MAX ?
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CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
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clockevents_notify(reason, &pr->id);
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}
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static void lapic_timer_propagate_broadcast(struct acpi_processor *pr)
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{
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smp_call_function_single(pr->id, __lapic_timer_propagate_broadcast,
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(void *)pr, 1);
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}
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/* Power(C) State timer broadcast control */
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static void lapic_timer_state_broadcast(struct acpi_processor *pr,
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struct acpi_processor_cx *cx,
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int broadcast)
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{
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int state = cx - pr->power.states;
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if (state >= pr->power.timer_broadcast_on_state) {
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unsigned long reason;
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reason = broadcast ? CLOCK_EVT_NOTIFY_BROADCAST_ENTER :
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CLOCK_EVT_NOTIFY_BROADCAST_EXIT;
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clockevents_notify(reason, &pr->id);
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}
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}
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#else
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static void lapic_timer_check_state(int state, struct acpi_processor *pr,
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struct acpi_processor_cx *cstate) { }
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static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) { }
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static void lapic_timer_state_broadcast(struct acpi_processor *pr,
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struct acpi_processor_cx *cx,
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int broadcast)
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{
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}
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#endif
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/*
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* Suspend / resume control
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*/
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static int acpi_idle_suspend;
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static u32 saved_bm_rld;
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static void acpi_idle_bm_rld_save(void)
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{
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acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &saved_bm_rld);
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}
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static void acpi_idle_bm_rld_restore(void)
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{
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u32 resumed_bm_rld;
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acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_RLD, &resumed_bm_rld);
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if (resumed_bm_rld != saved_bm_rld)
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acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, saved_bm_rld);
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}
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int acpi_processor_suspend(struct acpi_device * device, pm_message_t state)
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{
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if (acpi_idle_suspend == 1)
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return 0;
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acpi_idle_bm_rld_save();
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acpi_idle_suspend = 1;
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return 0;
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}
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int acpi_processor_resume(struct acpi_device * device)
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{
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if (acpi_idle_suspend == 0)
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return 0;
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acpi_idle_bm_rld_restore();
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acpi_idle_suspend = 0;
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return 0;
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}
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#if defined(CONFIG_X86)
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static void tsc_check_state(int state)
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{
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switch (boot_cpu_data.x86_vendor) {
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case X86_VENDOR_AMD:
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case X86_VENDOR_INTEL:
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/*
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* AMD Fam10h TSC will tick in all
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* C/P/S0/S1 states when this bit is set.
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*/
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if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
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return;
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/*FALL THROUGH*/
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default:
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/* TSC could halt in idle, so notify users */
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if (state > ACPI_STATE_C1)
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mark_tsc_unstable("TSC halts in idle");
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}
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}
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#else
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static void tsc_check_state(int state) { return; }
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#endif
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static int acpi_processor_get_power_info_fadt(struct acpi_processor *pr)
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{
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if (!pr)
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return -EINVAL;
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if (!pr->pblk)
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return -ENODEV;
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/* if info is obtained from pblk/fadt, type equals state */
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pr->power.states[ACPI_STATE_C2].type = ACPI_STATE_C2;
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pr->power.states[ACPI_STATE_C3].type = ACPI_STATE_C3;
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#ifndef CONFIG_HOTPLUG_CPU
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/*
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* Check for P_LVL2_UP flag before entering C2 and above on
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* an SMP system.
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*/
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if ((num_online_cpus() > 1) &&
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!(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
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return -ENODEV;
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#endif
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/* determine C2 and C3 address from pblk */
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pr->power.states[ACPI_STATE_C2].address = pr->pblk + 4;
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pr->power.states[ACPI_STATE_C3].address = pr->pblk + 5;
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/* determine latencies from FADT */
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pr->power.states[ACPI_STATE_C2].latency = acpi_gbl_FADT.C2latency;
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pr->power.states[ACPI_STATE_C3].latency = acpi_gbl_FADT.C3latency;
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/*
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* FADT specified C2 latency must be less than or equal to
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* 100 microseconds.
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*/
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if (acpi_gbl_FADT.C2latency > ACPI_PROCESSOR_MAX_C2_LATENCY) {
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ACPI_DEBUG_PRINT((ACPI_DB_INFO,
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"C2 latency too large [%d]\n", acpi_gbl_FADT.C2latency));
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/* invalidate C2 */
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pr->power.states[ACPI_STATE_C2].address = 0;
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}
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/*
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* FADT supplied C3 latency must be less than or equal to
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* 1000 microseconds.
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*/
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if (acpi_gbl_FADT.C3latency > ACPI_PROCESSOR_MAX_C3_LATENCY) {
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ACPI_DEBUG_PRINT((ACPI_DB_INFO,
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"C3 latency too large [%d]\n", acpi_gbl_FADT.C3latency));
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/* invalidate C3 */
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pr->power.states[ACPI_STATE_C3].address = 0;
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}
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ACPI_DEBUG_PRINT((ACPI_DB_INFO,
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"lvl2[0x%08x] lvl3[0x%08x]\n",
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pr->power.states[ACPI_STATE_C2].address,
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pr->power.states[ACPI_STATE_C3].address));
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return 0;
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}
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static int acpi_processor_get_power_info_default(struct acpi_processor *pr)
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{
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if (!pr->power.states[ACPI_STATE_C1].valid) {
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/* set the first C-State to C1 */
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/* all processors need to support C1 */
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pr->power.states[ACPI_STATE_C1].type = ACPI_STATE_C1;
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pr->power.states[ACPI_STATE_C1].valid = 1;
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pr->power.states[ACPI_STATE_C1].entry_method = ACPI_CSTATE_HALT;
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}
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/* the C0 state only exists as a filler in our array */
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pr->power.states[ACPI_STATE_C0].valid = 1;
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return 0;
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}
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static int acpi_processor_get_power_info_cst(struct acpi_processor *pr)
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{
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acpi_status status = 0;
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u64 count;
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int current_count;
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int i;
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struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
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union acpi_object *cst;
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|
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if (nocst)
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return -ENODEV;
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current_count = 0;
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status = acpi_evaluate_object(pr->handle, "_CST", NULL, &buffer);
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if (ACPI_FAILURE(status)) {
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ACPI_DEBUG_PRINT((ACPI_DB_INFO, "No _CST, giving up\n"));
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return -ENODEV;
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}
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cst = buffer.pointer;
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/* There must be at least 2 elements */
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if (!cst || (cst->type != ACPI_TYPE_PACKAGE) || cst->package.count < 2) {
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printk(KERN_ERR PREFIX "not enough elements in _CST\n");
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status = -EFAULT;
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goto end;
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}
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count = cst->package.elements[0].integer.value;
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/* Validate number of power states. */
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if (count < 1 || count != cst->package.count - 1) {
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printk(KERN_ERR PREFIX "count given by _CST is not valid\n");
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status = -EFAULT;
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goto end;
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}
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/* Tell driver that at least _CST is supported. */
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pr->flags.has_cst = 1;
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for (i = 1; i <= count; i++) {
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union acpi_object *element;
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union acpi_object *obj;
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struct acpi_power_register *reg;
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struct acpi_processor_cx cx;
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memset(&cx, 0, sizeof(cx));
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element = &(cst->package.elements[i]);
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if (element->type != ACPI_TYPE_PACKAGE)
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continue;
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if (element->package.count != 4)
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continue;
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obj = &(element->package.elements[0]);
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if (obj->type != ACPI_TYPE_BUFFER)
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continue;
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reg = (struct acpi_power_register *)obj->buffer.pointer;
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if (reg->space_id != ACPI_ADR_SPACE_SYSTEM_IO &&
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(reg->space_id != ACPI_ADR_SPACE_FIXED_HARDWARE))
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continue;
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/* There should be an easy way to extract an integer... */
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obj = &(element->package.elements[1]);
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if (obj->type != ACPI_TYPE_INTEGER)
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continue;
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cx.type = obj->integer.value;
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/*
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* Some buggy BIOSes won't list C1 in _CST -
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* Let acpi_processor_get_power_info_default() handle them later
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*/
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if (i == 1 && cx.type != ACPI_STATE_C1)
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current_count++;
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cx.address = reg->address;
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cx.index = current_count + 1;
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|
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cx.entry_method = ACPI_CSTATE_SYSTEMIO;
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if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE) {
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if (acpi_processor_ffh_cstate_probe
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(pr->id, &cx, reg) == 0) {
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cx.entry_method = ACPI_CSTATE_FFH;
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} else if (cx.type == ACPI_STATE_C1) {
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/*
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* C1 is a special case where FIXED_HARDWARE
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* can be handled in non-MWAIT way as well.
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* In that case, save this _CST entry info.
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* Otherwise, ignore this info and continue.
|
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*/
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cx.entry_method = ACPI_CSTATE_HALT;
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snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT");
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} else {
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continue;
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}
|
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if (cx.type == ACPI_STATE_C1 &&
|
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(boot_option_idle_override == IDLE_NOMWAIT)) {
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/*
|
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* In most cases the C1 space_id obtained from
|
|
* _CST object is FIXED_HARDWARE access mode.
|
|
* But when the option of idle=halt is added,
|
|
* the entry_method type should be changed from
|
|
* CSTATE_FFH to CSTATE_HALT.
|
|
* When the option of idle=nomwait is added,
|
|
* the C1 entry_method type should be
|
|
* CSTATE_HALT.
|
|
*/
|
|
cx.entry_method = ACPI_CSTATE_HALT;
|
|
snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI HLT");
|
|
}
|
|
} else {
|
|
snprintf(cx.desc, ACPI_CX_DESC_LEN, "ACPI IOPORT 0x%x",
|
|
cx.address);
|
|
}
|
|
|
|
if (cx.type == ACPI_STATE_C1) {
|
|
cx.valid = 1;
|
|
}
|
|
|
|
obj = &(element->package.elements[2]);
|
|
if (obj->type != ACPI_TYPE_INTEGER)
|
|
continue;
|
|
|
|
cx.latency = obj->integer.value;
|
|
|
|
obj = &(element->package.elements[3]);
|
|
if (obj->type != ACPI_TYPE_INTEGER)
|
|
continue;
|
|
|
|
cx.power = obj->integer.value;
|
|
|
|
current_count++;
|
|
memcpy(&(pr->power.states[current_count]), &cx, sizeof(cx));
|
|
|
|
/*
|
|
* We support total ACPI_PROCESSOR_MAX_POWER - 1
|
|
* (From 1 through ACPI_PROCESSOR_MAX_POWER - 1)
|
|
*/
|
|
if (current_count >= (ACPI_PROCESSOR_MAX_POWER - 1)) {
|
|
printk(KERN_WARNING
|
|
"Limiting number of power states to max (%d)\n",
|
|
ACPI_PROCESSOR_MAX_POWER);
|
|
printk(KERN_WARNING
|
|
"Please increase ACPI_PROCESSOR_MAX_POWER if needed.\n");
|
|
break;
|
|
}
|
|
}
|
|
|
|
ACPI_DEBUG_PRINT((ACPI_DB_INFO, "Found %d power states\n",
|
|
current_count));
|
|
|
|
/* Validate number of power states discovered */
|
|
if (current_count < 2)
|
|
status = -EFAULT;
|
|
|
|
end:
|
|
kfree(buffer.pointer);
|
|
|
|
return status;
|
|
}
|
|
|
|
static void acpi_processor_power_verify_c3(struct acpi_processor *pr,
|
|
struct acpi_processor_cx *cx)
|
|
{
|
|
static int bm_check_flag = -1;
|
|
static int bm_control_flag = -1;
|
|
|
|
|
|
if (!cx->address)
|
|
return;
|
|
|
|
/*
|
|
* PIIX4 Erratum #18: We don't support C3 when Type-F (fast)
|
|
* DMA transfers are used by any ISA device to avoid livelock.
|
|
* Note that we could disable Type-F DMA (as recommended by
|
|
* the erratum), but this is known to disrupt certain ISA
|
|
* devices thus we take the conservative approach.
|
|
*/
|
|
else if (errata.piix4.fdma) {
|
|
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
|
|
"C3 not supported on PIIX4 with Type-F DMA\n"));
|
|
return;
|
|
}
|
|
|
|
/* All the logic here assumes flags.bm_check is same across all CPUs */
|
|
if (bm_check_flag == -1) {
|
|
/* Determine whether bm_check is needed based on CPU */
|
|
acpi_processor_power_init_bm_check(&(pr->flags), pr->id);
|
|
bm_check_flag = pr->flags.bm_check;
|
|
bm_control_flag = pr->flags.bm_control;
|
|
} else {
|
|
pr->flags.bm_check = bm_check_flag;
|
|
pr->flags.bm_control = bm_control_flag;
|
|
}
|
|
|
|
if (pr->flags.bm_check) {
|
|
if (!pr->flags.bm_control) {
|
|
if (pr->flags.has_cst != 1) {
|
|
/* bus mastering control is necessary */
|
|
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
|
|
"C3 support requires BM control\n"));
|
|
return;
|
|
} else {
|
|
/* Here we enter C3 without bus mastering */
|
|
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
|
|
"C3 support without BM control\n"));
|
|
}
|
|
}
|
|
} else {
|
|
/*
|
|
* WBINVD should be set in fadt, for C3 state to be
|
|
* supported on when bm_check is not required.
|
|
*/
|
|
if (!(acpi_gbl_FADT.flags & ACPI_FADT_WBINVD)) {
|
|
ACPI_DEBUG_PRINT((ACPI_DB_INFO,
|
|
"Cache invalidation should work properly"
|
|
" for C3 to be enabled on SMP systems\n"));
|
|
return;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Otherwise we've met all of our C3 requirements.
|
|
* Normalize the C3 latency to expidite policy. Enable
|
|
* checking of bus mastering status (bm_check) so we can
|
|
* use this in our C3 policy
|
|
*/
|
|
cx->valid = 1;
|
|
|
|
cx->latency_ticks = cx->latency;
|
|
/*
|
|
* On older chipsets, BM_RLD needs to be set
|
|
* in order for Bus Master activity to wake the
|
|
* system from C3. Newer chipsets handle DMA
|
|
* during C3 automatically and BM_RLD is a NOP.
|
|
* In either case, the proper way to
|
|
* handle BM_RLD is to set it and leave it set.
|
|
*/
|
|
acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 1);
|
|
|
|
return;
|
|
}
|
|
|
|
static int acpi_processor_power_verify(struct acpi_processor *pr)
|
|
{
|
|
unsigned int i;
|
|
unsigned int working = 0;
|
|
|
|
pr->power.timer_broadcast_on_state = INT_MAX;
|
|
|
|
for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) {
|
|
struct acpi_processor_cx *cx = &pr->power.states[i];
|
|
|
|
switch (cx->type) {
|
|
case ACPI_STATE_C1:
|
|
cx->valid = 1;
|
|
break;
|
|
|
|
case ACPI_STATE_C2:
|
|
if (!cx->address)
|
|
break;
|
|
cx->valid = 1;
|
|
cx->latency_ticks = cx->latency; /* Normalize latency */
|
|
break;
|
|
|
|
case ACPI_STATE_C3:
|
|
acpi_processor_power_verify_c3(pr, cx);
|
|
break;
|
|
}
|
|
if (!cx->valid)
|
|
continue;
|
|
|
|
lapic_timer_check_state(i, pr, cx);
|
|
tsc_check_state(cx->type);
|
|
working++;
|
|
}
|
|
|
|
lapic_timer_propagate_broadcast(pr);
|
|
|
|
return (working);
|
|
}
|
|
|
|
static int acpi_processor_get_power_info(struct acpi_processor *pr)
|
|
{
|
|
unsigned int i;
|
|
int result;
|
|
|
|
|
|
/* NOTE: the idle thread may not be running while calling
|
|
* this function */
|
|
|
|
/* Zero initialize all the C-states info. */
|
|
memset(pr->power.states, 0, sizeof(pr->power.states));
|
|
|
|
result = acpi_processor_get_power_info_cst(pr);
|
|
if (result == -ENODEV)
|
|
result = acpi_processor_get_power_info_fadt(pr);
|
|
|
|
if (result)
|
|
return result;
|
|
|
|
acpi_processor_get_power_info_default(pr);
|
|
|
|
pr->power.count = acpi_processor_power_verify(pr);
|
|
|
|
/*
|
|
* if one state of type C2 or C3 is available, mark this
|
|
* CPU as being "idle manageable"
|
|
*/
|
|
for (i = 1; i < ACPI_PROCESSOR_MAX_POWER; i++) {
|
|
if (pr->power.states[i].valid) {
|
|
pr->power.count = i;
|
|
if (pr->power.states[i].type >= ACPI_STATE_C2)
|
|
pr->flags.power = 1;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* acpi_idle_bm_check - checks if bus master activity was detected
|
|
*/
|
|
static int acpi_idle_bm_check(void)
|
|
{
|
|
u32 bm_status = 0;
|
|
|
|
if (bm_check_disable)
|
|
return 0;
|
|
|
|
acpi_read_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, &bm_status);
|
|
if (bm_status)
|
|
acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_STATUS, 1);
|
|
/*
|
|
* PIIX4 Erratum #18: Note that BM_STS doesn't always reflect
|
|
* the true state of bus mastering activity; forcing us to
|
|
* manually check the BMIDEA bit of each IDE channel.
|
|
*/
|
|
else if (errata.piix4.bmisx) {
|
|
if ((inb_p(errata.piix4.bmisx + 0x02) & 0x01)
|
|
|| (inb_p(errata.piix4.bmisx + 0x0A) & 0x01))
|
|
bm_status = 1;
|
|
}
|
|
return bm_status;
|
|
}
|
|
|
|
/**
|
|
* acpi_idle_do_entry - a helper function that does C2 and C3 type entry
|
|
* @cx: cstate data
|
|
*
|
|
* Caller disables interrupt before call and enables interrupt after return.
|
|
*/
|
|
static inline void acpi_idle_do_entry(struct acpi_processor_cx *cx)
|
|
{
|
|
/* Don't trace irqs off for idle */
|
|
stop_critical_timings();
|
|
if (cx->entry_method == ACPI_CSTATE_FFH) {
|
|
/* Call into architectural FFH based C-state */
|
|
acpi_processor_ffh_cstate_enter(cx);
|
|
} else if (cx->entry_method == ACPI_CSTATE_HALT) {
|
|
acpi_safe_halt();
|
|
} else {
|
|
/* IO port based C-state */
|
|
inb(cx->address);
|
|
/* Dummy wait op - must do something useless after P_LVL2 read
|
|
because chipsets cannot guarantee that STPCLK# signal
|
|
gets asserted in time to freeze execution properly. */
|
|
inl(acpi_gbl_FADT.xpm_timer_block.address);
|
|
}
|
|
start_critical_timings();
|
|
}
|
|
|
|
/**
|
|
* acpi_idle_enter_c1 - enters an ACPI C1 state-type
|
|
* @dev: the target CPU
|
|
* @state: the state data
|
|
*
|
|
* This is equivalent to the HALT instruction.
|
|
*/
|
|
static int acpi_idle_enter_c1(struct cpuidle_device *dev,
|
|
struct cpuidle_state *state)
|
|
{
|
|
ktime_t kt1, kt2;
|
|
s64 idle_time;
|
|
struct acpi_processor *pr;
|
|
struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
|
|
|
|
pr = __this_cpu_read(processors);
|
|
|
|
if (unlikely(!pr))
|
|
return 0;
|
|
|
|
local_irq_disable();
|
|
|
|
/* Do not access any ACPI IO ports in suspend path */
|
|
if (acpi_idle_suspend) {
|
|
local_irq_enable();
|
|
cpu_relax();
|
|
return 0;
|
|
}
|
|
|
|
lapic_timer_state_broadcast(pr, cx, 1);
|
|
kt1 = ktime_get_real();
|
|
acpi_idle_do_entry(cx);
|
|
kt2 = ktime_get_real();
|
|
idle_time = ktime_to_us(ktime_sub(kt2, kt1));
|
|
|
|
local_irq_enable();
|
|
cx->usage++;
|
|
lapic_timer_state_broadcast(pr, cx, 0);
|
|
|
|
return idle_time;
|
|
}
|
|
|
|
/**
|
|
* acpi_idle_enter_simple - enters an ACPI state without BM handling
|
|
* @dev: the target CPU
|
|
* @state: the state data
|
|
*/
|
|
static int acpi_idle_enter_simple(struct cpuidle_device *dev,
|
|
struct cpuidle_state *state)
|
|
{
|
|
struct acpi_processor *pr;
|
|
struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
|
|
ktime_t kt1, kt2;
|
|
s64 idle_time_ns;
|
|
s64 idle_time;
|
|
|
|
pr = __this_cpu_read(processors);
|
|
|
|
if (unlikely(!pr))
|
|
return 0;
|
|
|
|
if (acpi_idle_suspend)
|
|
return(acpi_idle_enter_c1(dev, state));
|
|
|
|
local_irq_disable();
|
|
|
|
if (cx->entry_method != ACPI_CSTATE_FFH) {
|
|
current_thread_info()->status &= ~TS_POLLING;
|
|
/*
|
|
* TS_POLLING-cleared state must be visible before we test
|
|
* NEED_RESCHED:
|
|
*/
|
|
smp_mb();
|
|
|
|
if (unlikely(need_resched())) {
|
|
current_thread_info()->status |= TS_POLLING;
|
|
local_irq_enable();
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Must be done before busmaster disable as we might need to
|
|
* access HPET !
|
|
*/
|
|
lapic_timer_state_broadcast(pr, cx, 1);
|
|
|
|
if (cx->type == ACPI_STATE_C3)
|
|
ACPI_FLUSH_CPU_CACHE();
|
|
|
|
kt1 = ktime_get_real();
|
|
/* Tell the scheduler that we are going deep-idle: */
|
|
sched_clock_idle_sleep_event();
|
|
acpi_idle_do_entry(cx);
|
|
kt2 = ktime_get_real();
|
|
idle_time_ns = ktime_to_ns(ktime_sub(kt2, kt1));
|
|
idle_time = idle_time_ns;
|
|
do_div(idle_time, NSEC_PER_USEC);
|
|
|
|
/* Tell the scheduler how much we idled: */
|
|
sched_clock_idle_wakeup_event(idle_time_ns);
|
|
|
|
local_irq_enable();
|
|
if (cx->entry_method != ACPI_CSTATE_FFH)
|
|
current_thread_info()->status |= TS_POLLING;
|
|
|
|
cx->usage++;
|
|
|
|
lapic_timer_state_broadcast(pr, cx, 0);
|
|
cx->time += idle_time;
|
|
return idle_time;
|
|
}
|
|
|
|
static int c3_cpu_count;
|
|
static DEFINE_SPINLOCK(c3_lock);
|
|
|
|
/**
|
|
* acpi_idle_enter_bm - enters C3 with proper BM handling
|
|
* @dev: the target CPU
|
|
* @state: the state data
|
|
*
|
|
* If BM is detected, the deepest non-C3 idle state is entered instead.
|
|
*/
|
|
static int acpi_idle_enter_bm(struct cpuidle_device *dev,
|
|
struct cpuidle_state *state)
|
|
{
|
|
struct acpi_processor *pr;
|
|
struct acpi_processor_cx *cx = cpuidle_get_statedata(state);
|
|
ktime_t kt1, kt2;
|
|
s64 idle_time_ns;
|
|
s64 idle_time;
|
|
|
|
|
|
pr = __this_cpu_read(processors);
|
|
|
|
if (unlikely(!pr))
|
|
return 0;
|
|
|
|
if (acpi_idle_suspend)
|
|
return(acpi_idle_enter_c1(dev, state));
|
|
|
|
if (!cx->bm_sts_skip && acpi_idle_bm_check()) {
|
|
if (dev->safe_state) {
|
|
dev->last_state = dev->safe_state;
|
|
return dev->safe_state->enter(dev, dev->safe_state);
|
|
} else {
|
|
local_irq_disable();
|
|
acpi_safe_halt();
|
|
local_irq_enable();
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
local_irq_disable();
|
|
|
|
if (cx->entry_method != ACPI_CSTATE_FFH) {
|
|
current_thread_info()->status &= ~TS_POLLING;
|
|
/*
|
|
* TS_POLLING-cleared state must be visible before we test
|
|
* NEED_RESCHED:
|
|
*/
|
|
smp_mb();
|
|
|
|
if (unlikely(need_resched())) {
|
|
current_thread_info()->status |= TS_POLLING;
|
|
local_irq_enable();
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
acpi_unlazy_tlb(smp_processor_id());
|
|
|
|
/* Tell the scheduler that we are going deep-idle: */
|
|
sched_clock_idle_sleep_event();
|
|
/*
|
|
* Must be done before busmaster disable as we might need to
|
|
* access HPET !
|
|
*/
|
|
lapic_timer_state_broadcast(pr, cx, 1);
|
|
|
|
kt1 = ktime_get_real();
|
|
/*
|
|
* disable bus master
|
|
* bm_check implies we need ARB_DIS
|
|
* !bm_check implies we need cache flush
|
|
* bm_control implies whether we can do ARB_DIS
|
|
*
|
|
* That leaves a case where bm_check is set and bm_control is
|
|
* not set. In that case we cannot do much, we enter C3
|
|
* without doing anything.
|
|
*/
|
|
if (pr->flags.bm_check && pr->flags.bm_control) {
|
|
spin_lock(&c3_lock);
|
|
c3_cpu_count++;
|
|
/* Disable bus master arbitration when all CPUs are in C3 */
|
|
if (c3_cpu_count == num_online_cpus())
|
|
acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1);
|
|
spin_unlock(&c3_lock);
|
|
} else if (!pr->flags.bm_check) {
|
|
ACPI_FLUSH_CPU_CACHE();
|
|
}
|
|
|
|
acpi_idle_do_entry(cx);
|
|
|
|
/* Re-enable bus master arbitration */
|
|
if (pr->flags.bm_check && pr->flags.bm_control) {
|
|
spin_lock(&c3_lock);
|
|
acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0);
|
|
c3_cpu_count--;
|
|
spin_unlock(&c3_lock);
|
|
}
|
|
kt2 = ktime_get_real();
|
|
idle_time_ns = ktime_to_ns(ktime_sub(kt2, kt1));
|
|
idle_time = idle_time_ns;
|
|
do_div(idle_time, NSEC_PER_USEC);
|
|
|
|
/* Tell the scheduler how much we idled: */
|
|
sched_clock_idle_wakeup_event(idle_time_ns);
|
|
|
|
local_irq_enable();
|
|
if (cx->entry_method != ACPI_CSTATE_FFH)
|
|
current_thread_info()->status |= TS_POLLING;
|
|
|
|
cx->usage++;
|
|
|
|
lapic_timer_state_broadcast(pr, cx, 0);
|
|
cx->time += idle_time;
|
|
return idle_time;
|
|
}
|
|
|
|
struct cpuidle_driver acpi_idle_driver = {
|
|
.name = "acpi_idle",
|
|
.owner = THIS_MODULE,
|
|
};
|
|
|
|
/**
|
|
* acpi_processor_setup_cpuidle - prepares and configures CPUIDLE
|
|
* @pr: the ACPI processor
|
|
*/
|
|
static int acpi_processor_setup_cpuidle(struct acpi_processor *pr)
|
|
{
|
|
int i, count = CPUIDLE_DRIVER_STATE_START;
|
|
struct acpi_processor_cx *cx;
|
|
struct cpuidle_state *state;
|
|
struct cpuidle_device *dev = &pr->power.dev;
|
|
|
|
if (!pr->flags.power_setup_done)
|
|
return -EINVAL;
|
|
|
|
if (pr->flags.power == 0) {
|
|
return -EINVAL;
|
|
}
|
|
|
|
dev->cpu = pr->id;
|
|
for (i = 0; i < CPUIDLE_STATE_MAX; i++) {
|
|
dev->states[i].name[0] = '\0';
|
|
dev->states[i].desc[0] = '\0';
|
|
}
|
|
|
|
if (max_cstate == 0)
|
|
max_cstate = 1;
|
|
|
|
for (i = 1; i < ACPI_PROCESSOR_MAX_POWER && i <= max_cstate; i++) {
|
|
cx = &pr->power.states[i];
|
|
state = &dev->states[count];
|
|
|
|
if (!cx->valid)
|
|
continue;
|
|
|
|
#ifdef CONFIG_HOTPLUG_CPU
|
|
if ((cx->type != ACPI_STATE_C1) && (num_online_cpus() > 1) &&
|
|
!pr->flags.has_cst &&
|
|
!(acpi_gbl_FADT.flags & ACPI_FADT_C2_MP_SUPPORTED))
|
|
continue;
|
|
#endif
|
|
cpuidle_set_statedata(state, cx);
|
|
|
|
snprintf(state->name, CPUIDLE_NAME_LEN, "C%d", i);
|
|
strncpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
|
|
state->exit_latency = cx->latency;
|
|
state->target_residency = cx->latency * latency_factor;
|
|
|
|
state->flags = 0;
|
|
switch (cx->type) {
|
|
case ACPI_STATE_C1:
|
|
if (cx->entry_method == ACPI_CSTATE_FFH)
|
|
state->flags |= CPUIDLE_FLAG_TIME_VALID;
|
|
|
|
state->enter = acpi_idle_enter_c1;
|
|
dev->safe_state = state;
|
|
break;
|
|
|
|
case ACPI_STATE_C2:
|
|
state->flags |= CPUIDLE_FLAG_TIME_VALID;
|
|
state->enter = acpi_idle_enter_simple;
|
|
dev->safe_state = state;
|
|
break;
|
|
|
|
case ACPI_STATE_C3:
|
|
state->flags |= CPUIDLE_FLAG_TIME_VALID;
|
|
state->enter = pr->flags.bm_check ?
|
|
acpi_idle_enter_bm :
|
|
acpi_idle_enter_simple;
|
|
break;
|
|
}
|
|
|
|
count++;
|
|
if (count == CPUIDLE_STATE_MAX)
|
|
break;
|
|
}
|
|
|
|
dev->state_count = count;
|
|
|
|
if (!count)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int acpi_processor_cst_has_changed(struct acpi_processor *pr)
|
|
{
|
|
int ret = 0;
|
|
|
|
if (disabled_by_idle_boot_param())
|
|
return 0;
|
|
|
|
if (!pr)
|
|
return -EINVAL;
|
|
|
|
if (nocst) {
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (!pr->flags.power_setup_done)
|
|
return -ENODEV;
|
|
|
|
cpuidle_pause_and_lock();
|
|
cpuidle_disable_device(&pr->power.dev);
|
|
acpi_processor_get_power_info(pr);
|
|
if (pr->flags.power) {
|
|
acpi_processor_setup_cpuidle(pr);
|
|
ret = cpuidle_enable_device(&pr->power.dev);
|
|
}
|
|
cpuidle_resume_and_unlock();
|
|
|
|
return ret;
|
|
}
|
|
|
|
int __cpuinit acpi_processor_power_init(struct acpi_processor *pr,
|
|
struct acpi_device *device)
|
|
{
|
|
acpi_status status = 0;
|
|
static int first_run;
|
|
|
|
if (disabled_by_idle_boot_param())
|
|
return 0;
|
|
|
|
if (!first_run) {
|
|
dmi_check_system(processor_power_dmi_table);
|
|
max_cstate = acpi_processor_cstate_check(max_cstate);
|
|
if (max_cstate < ACPI_C_STATES_MAX)
|
|
printk(KERN_NOTICE
|
|
"ACPI: processor limited to max C-state %d\n",
|
|
max_cstate);
|
|
first_run++;
|
|
}
|
|
|
|
if (!pr)
|
|
return -EINVAL;
|
|
|
|
if (acpi_gbl_FADT.cst_control && !nocst) {
|
|
status =
|
|
acpi_os_write_port(acpi_gbl_FADT.smi_command, acpi_gbl_FADT.cst_control, 8);
|
|
if (ACPI_FAILURE(status)) {
|
|
ACPI_EXCEPTION((AE_INFO, status,
|
|
"Notifying BIOS of _CST ability failed"));
|
|
}
|
|
}
|
|
|
|
acpi_processor_get_power_info(pr);
|
|
pr->flags.power_setup_done = 1;
|
|
|
|
/*
|
|
* Install the idle handler if processor power management is supported.
|
|
* Note that we use previously set idle handler will be used on
|
|
* platforms that only support C1.
|
|
*/
|
|
if (pr->flags.power) {
|
|
acpi_processor_setup_cpuidle(pr);
|
|
if (cpuidle_register_device(&pr->power.dev))
|
|
return -EIO;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int acpi_processor_power_exit(struct acpi_processor *pr,
|
|
struct acpi_device *device)
|
|
{
|
|
if (disabled_by_idle_boot_param())
|
|
return 0;
|
|
|
|
cpuidle_unregister_device(&pr->power.dev);
|
|
pr->flags.power_setup_done = 0;
|
|
|
|
return 0;
|
|
}
|