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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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770a1ad557
Add support for reading module EEPROMs through phylink. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
149 lines
5.1 KiB
C
149 lines
5.1 KiB
C
#ifndef NETDEV_PCS_H
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#define NETDEV_PCS_H
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#include <linux/phy.h>
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#include <linux/spinlock.h>
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#include <linux/workqueue.h>
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struct device_node;
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struct ethtool_cmd;
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struct net_device;
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enum {
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MLO_PAUSE_NONE,
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MLO_PAUSE_ASYM = BIT(0),
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MLO_PAUSE_SYM = BIT(1),
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MLO_PAUSE_RX = BIT(2),
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MLO_PAUSE_TX = BIT(3),
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MLO_PAUSE_TXRX_MASK = MLO_PAUSE_TX | MLO_PAUSE_RX,
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MLO_PAUSE_AN = BIT(4),
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MLO_AN_PHY = 0, /* Conventional PHY */
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MLO_AN_FIXED, /* Fixed-link mode */
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MLO_AN_SGMII, /* Cisco SGMII protocol */
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MLO_AN_8023Z, /* 1000base-X protocol */
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};
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static inline bool phylink_autoneg_inband(unsigned int mode)
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{
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return mode == MLO_AN_SGMII || mode == MLO_AN_8023Z;
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}
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struct phylink_link_state {
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__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
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__ETHTOOL_DECLARE_LINK_MODE_MASK(lp_advertising);
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phy_interface_t interface; /* PHY_INTERFACE_xxx */
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int speed;
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int duplex;
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int pause;
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unsigned int link:1;
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unsigned int an_enabled:1;
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unsigned int an_complete:1;
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};
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struct phylink_mac_ops {
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/**
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* validate: validate and update the link configuration
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* @ndev: net_device structure associated with MAC
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* @config: configuration to validate
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*
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* Update the %config->supported and %config->advertised masks
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* clearing bits that can not be supported.
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*
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* Note: the PHY may be able to transform from one connection
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* technology to another, so, eg, don't clear 1000BaseX just
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* because the MAC is unable to support it. This is more about
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* clearing unsupported speeds and duplex settings.
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*
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* If the %config->interface mode is %PHY_INTERFACE_MODE_1000BASEX
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* or %PHY_INTERFACE_MODE_2500BASEX, select the appropriate mode
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* based on %config->advertised and/or %config->speed.
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*/
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void (*validate)(struct net_device *ndev, unsigned long *supported,
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struct phylink_link_state *state);
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/* Read the current link state from the hardware */
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int (*mac_link_state)(struct net_device *, struct phylink_link_state *);
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/* Configure the MAC */
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/**
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* mac_config: configure the MAC for the selected mode and state
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* @ndev: net_device structure for the MAC
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* @mode: one of MLO_AN_FIXED, MLO_AN_PHY, MLO_AN_8023Z, MLO_AN_SGMII
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* @state: state structure
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*
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* The action performed depends on the currently selected mode:
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*
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* %MLO_AN_FIXED, %MLO_AN_PHY:
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* set the specified speed, duplex, pause mode, and phy interface
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* mode in the provided @state.
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* %MLO_AN_8023Z:
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* place the link in 1000base-X mode, advertising the parameters
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* given in advertising in @state.
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* %MLO_AN_SGMII:
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* place the link in Cisco SGMII mode - there is no advertisment
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* to make as the PHY communicates the speed and duplex to the
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* MAC over the in-band control word. Configuration of the pause
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* mode is as per MLO_AN_PHY since this is not included.
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*/
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void (*mac_config)(struct net_device *ndev, unsigned int mode,
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const struct phylink_link_state *state);
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/**
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* mac_an_restart: restart 802.3z BaseX autonegotiation
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* @ndev: net_device structure for the MAC
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*/
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void (*mac_an_restart)(struct net_device *ndev);
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void (*mac_link_down)(struct net_device *, unsigned int mode);
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void (*mac_link_up)(struct net_device *, unsigned int mode,
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struct phy_device *);
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};
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struct phylink *phylink_create(struct net_device *, struct device_node *,
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phy_interface_t iface, const struct phylink_mac_ops *ops);
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void phylink_destroy(struct phylink *);
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int phylink_connect_phy(struct phylink *, struct phy_device *);
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int phylink_of_phy_connect(struct phylink *, struct device_node *);
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void phylink_disconnect_phy(struct phylink *);
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void phylink_mac_change(struct phylink *, bool up);
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void phylink_start(struct phylink *);
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void phylink_stop(struct phylink *);
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void phylink_ethtool_get_wol(struct phylink *, struct ethtool_wolinfo *);
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int phylink_ethtool_set_wol(struct phylink *, struct ethtool_wolinfo *);
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int phylink_ethtool_ksettings_get(struct phylink *,
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struct ethtool_link_ksettings *);
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int phylink_ethtool_ksettings_set(struct phylink *,
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const struct ethtool_link_ksettings *);
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int phylink_ethtool_nway_reset(struct phylink *);
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void phylink_ethtool_get_pauseparam(struct phylink *,
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struct ethtool_pauseparam *);
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int phylink_ethtool_set_pauseparam(struct phylink *,
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struct ethtool_pauseparam *);
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int phylink_ethtool_get_module_info(struct phylink *, struct ethtool_modinfo *);
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int phylink_ethtool_get_module_eeprom(struct phylink *,
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struct ethtool_eeprom *, u8 *);
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int phylink_init_eee(struct phylink *, bool);
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int phylink_get_eee_err(struct phylink *);
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int phylink_ethtool_get_eee(struct phylink *, struct ethtool_eee *);
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int phylink_ethtool_set_eee(struct phylink *, struct ethtool_eee *);
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int phylink_mii_ioctl(struct phylink *, struct ifreq *, int);
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#define phylink_zero(bm) \
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bitmap_zero(bm, __ETHTOOL_LINK_MODE_MASK_NBITS)
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#define __phylink_do_bit(op, bm, mode) \
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op(ETHTOOL_LINK_MODE_ ## mode ## _BIT, bm)
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#define phylink_set(bm, mode) __phylink_do_bit(__set_bit, bm, mode)
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#define phylink_clear(bm, mode) __phylink_do_bit(__clear_bit, bm, mode)
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#define phylink_test(bm, mode) __phylink_do_bit(test_bit, bm, mode)
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void phylink_set_port_modes(unsigned long *bits);
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#endif
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