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fdd8b079e3
Symbols like SOFT_RESET are way too generic to be exported at large. To avoid this, let's move the mbus bridge register defines into a separate file and include it where needed. This affects mach-kirkwood, mach-loki, mach-mv78xx0 and mach-orion5x simultaneously as they all share code in plat-orion which relies on those defines. Some other defines have been moved to narrower scopes, or simply deleted when they had no user. This fixes compilation problem with mpt2sas on the above listed platforms. Signed-off-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
84 lines
2.3 KiB
C
84 lines
2.3 KiB
C
/*
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* arch/arm/mach-loki/include/mach/loki.h
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*
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* Generic definitions for Marvell Loki (88RC8480) SoC flavors
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_LOKI_H
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#define __ASM_ARCH_LOKI_H
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/*
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* Marvell Loki (88RC8480) address maps.
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*
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* phys
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* d0000000 on-chip peripheral registers
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* e0000000 PCIe 0 Memory space
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* e8000000 PCIe 1 Memory space
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* f0000000 PCIe 0 I/O space
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* f0100000 PCIe 1 I/O space
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*
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* virt phys size
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* fed00000 d0000000 1M on-chip peripheral registers
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* fee00000 f0000000 64K PCIe 0 I/O space
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* fef00000 f0100000 64K PCIe 1 I/O space
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*/
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#define LOKI_REGS_PHYS_BASE 0xd0000000
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#define LOKI_REGS_VIRT_BASE 0xfed00000
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#define LOKI_REGS_SIZE SZ_1M
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#define LOKI_PCIE0_IO_PHYS_BASE 0xf0000000
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#define LOKI_PCIE0_IO_VIRT_BASE 0xfee00000
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#define LOKI_PCIE0_IO_BUS_BASE 0x00000000
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#define LOKI_PCIE0_IO_SIZE SZ_64K
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#define LOKI_PCIE1_IO_PHYS_BASE 0xf0100000
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#define LOKI_PCIE1_IO_VIRT_BASE 0xfef00000
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#define LOKI_PCIE1_IO_BUS_BASE 0x00000000
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#define LOKI_PCIE1_IO_SIZE SZ_64K
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#define LOKI_PCIE0_MEM_PHYS_BASE 0xe0000000
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#define LOKI_PCIE0_MEM_SIZE SZ_128M
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#define LOKI_PCIE1_MEM_PHYS_BASE 0xe8000000
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#define LOKI_PCIE1_MEM_SIZE SZ_128M
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/*
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* Register Map
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*/
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#define DEV_BUS_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x10000)
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#define DEV_BUS_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x10000)
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#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
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#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
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#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
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#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
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#define BRIDGE_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x20000)
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#define PCIE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x30000)
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#define PCIE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x40000)
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#define SAS0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x80000)
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#define SAS1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x90000)
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#define GE0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xa0000)
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#define GE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xa0000)
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#define GE1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xb0000)
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#define GE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xb0000)
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#define DDR_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xf0000)
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#define DDR_REG(x) (DDR_VIRT_BASE | (x))
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#define GPIO_MAX 8
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#endif
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