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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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23bdf86aa0
Patch from Lennert Buytenhek This patch adds support for the new XScale v3 core. This is an ARMv5 ISA core with the following additions: - L2 cache - I/O coherency support (on select chipsets) - Low-Locality Reference cache attributes (replaces mini-cache) - Supersections (v6 compatible) - 36-bit addressing (v6 compatible) - Single instruction cache line clean/invalidate - LRU cache replacement (vs round-robin) I attempted to merge the XSC3 support into proc-xscale.S, but XSC3 cores have separate errata and have to handle things like L2, so it is simpler to keep it separate. L2 cache support is currently a build option because the L2 enable bit must be set before we enable the MMU and there is no easy way to capture command line parameters at this point. There are still optimizations that can be done such as using LLR for copypage (in theory using the exisiting mini-cache code) but those can be addressed down the road. Signed-off-by: Deepak Saxena <dsaxena@plexity.net> Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
194 lines
4.2 KiB
C
194 lines
4.2 KiB
C
/*
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* linux/include/asm-arm/page.h
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*
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* Copyright (C) 1995-2003 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASMARM_PAGE_H
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#define _ASMARM_PAGE_H
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#include <linux/config.h>
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/* PAGE_SHIFT determines the page size */
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#define PAGE_SHIFT 12
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#define PAGE_SIZE (1UL << PAGE_SHIFT)
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#define PAGE_MASK (~(PAGE_SIZE-1))
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#ifdef __KERNEL__
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/* to align the pointer to the (next) page boundary */
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#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK)
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#ifndef __ASSEMBLY__
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#include <asm/glue.h>
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/*
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* User Space Model
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* ================
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*
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* This section selects the correct set of functions for dealing with
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* page-based copying and clearing for user space for the particular
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* processor(s) we're building for.
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*
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* We have the following to choose from:
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* v3 - ARMv3
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* v4wt - ARMv4 with writethrough cache, without minicache
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* v4wb - ARMv4 with writeback cache, without minicache
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* v4_mc - ARMv4 with minicache
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* xscale - Xscale
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* xsc3 - XScalev3
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*/
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#undef _USER
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#undef MULTI_USER
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#ifdef CONFIG_CPU_COPY_V3
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# ifdef _USER
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# define MULTI_USER 1
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# else
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# define _USER v3
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# endif
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#endif
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#ifdef CONFIG_CPU_COPY_V4WT
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# ifdef _USER
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# define MULTI_USER 1
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# else
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# define _USER v4wt
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# endif
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#endif
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#ifdef CONFIG_CPU_COPY_V4WB
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# ifdef _USER
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# define MULTI_USER 1
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# else
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# define _USER v4wb
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# endif
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#endif
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#ifdef CONFIG_CPU_SA1100
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# ifdef _USER
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# define MULTI_USER 1
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# else
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# define _USER v4_mc
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# endif
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#endif
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#ifdef CONFIG_CPU_XSCALE
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# ifdef _USER
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# define MULTI_USER 1
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# else
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# define _USER xscale_mc
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# endif
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#endif
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#ifdef CONFIG_CPU_XSC3
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# ifdef _USER
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# define MULTI_USER 1
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# else
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# define _USER xsc3_mc
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# endif
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#endif
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#ifdef CONFIG_CPU_COPY_V6
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# define MULTI_USER 1
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#endif
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#if !defined(_USER) && !defined(MULTI_USER)
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#error Unknown user operations model
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#endif
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struct cpu_user_fns {
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void (*cpu_clear_user_page)(void *p, unsigned long user);
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void (*cpu_copy_user_page)(void *to, const void *from,
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unsigned long user);
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};
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#ifdef MULTI_USER
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extern struct cpu_user_fns cpu_user;
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#define __cpu_clear_user_page cpu_user.cpu_clear_user_page
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#define __cpu_copy_user_page cpu_user.cpu_copy_user_page
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#else
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#define __cpu_clear_user_page __glue(_USER,_clear_user_page)
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#define __cpu_copy_user_page __glue(_USER,_copy_user_page)
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extern void __cpu_clear_user_page(void *p, unsigned long user);
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extern void __cpu_copy_user_page(void *to, const void *from,
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unsigned long user);
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#endif
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#define clear_user_page(addr,vaddr,pg) __cpu_clear_user_page(addr, vaddr)
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#define copy_user_page(to,from,vaddr,pg) __cpu_copy_user_page(to, from, vaddr)
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#define clear_page(page) memzero((void *)(page), PAGE_SIZE)
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extern void copy_page(void *to, const void *from);
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#undef STRICT_MM_TYPECHECKS
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#ifdef STRICT_MM_TYPECHECKS
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/*
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* These are used to make use of C type-checking..
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*/
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typedef struct { unsigned long pte; } pte_t;
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typedef struct { unsigned long pmd; } pmd_t;
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typedef struct { unsigned long pgd[2]; } pgd_t;
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typedef struct { unsigned long pgprot; } pgprot_t;
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#define pte_val(x) ((x).pte)
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#define pmd_val(x) ((x).pmd)
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#define pgd_val(x) ((x).pgd[0])
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#define pgprot_val(x) ((x).pgprot)
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#define __pte(x) ((pte_t) { (x) } )
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#define __pmd(x) ((pmd_t) { (x) } )
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#define __pgprot(x) ((pgprot_t) { (x) } )
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#else
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/*
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* .. while these make it easier on the compiler
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*/
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typedef unsigned long pte_t;
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typedef unsigned long pmd_t;
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typedef unsigned long pgd_t[2];
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typedef unsigned long pgprot_t;
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#define pte_val(x) (x)
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#define pmd_val(x) (x)
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#define pgd_val(x) ((x)[0])
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#define pgprot_val(x) (x)
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#define __pte(x) (x)
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#define __pmd(x) (x)
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#define __pgprot(x) (x)
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#endif /* STRICT_MM_TYPECHECKS */
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/* the upper-most page table pointer */
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extern pmd_t *top_pmd;
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#include <asm/memory.h>
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#endif /* !__ASSEMBLY__ */
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#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
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VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
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/*
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* With EABI on ARMv5 and above we must have 64-bit aligned slab pointers.
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*/
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#if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
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#define ARCH_SLAB_MINALIGN 8
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#endif
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#endif /* __KERNEL__ */
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#include <asm-generic/page.h>
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#endif
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