Anup Patel 2bc3fc877a RISC-V: Remove CLINT related code from timer and arch ... Right now the RISC-V timer driver is convoluted to support: 1. Linux RISC-V S-mode (with MMU) where it will use TIME CSR for clocksource and SBI timer calls for clockevent device. 2. Linux RISC-V M-mode (without MMU) where it will use CLINT MMIO counter register for clocksource and CLINT MMIO compare register for clockevent device. We now have a separate CLINT timer driver which also provide CLINT based IPI operations so let's remove CLINT MMIO related code from arch/riscv directory and RISC-V timer driver. Signed-off-by: Anup Patel <anup.patel@wdc.com> Tested-by: Emil Renner Berhing <kernel@esmil.dk> Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2020-08-20 10:58:13 -07:00
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vdso
.gitignore
asm-offsets.c
cacheinfo.c
cpu_ops_sbi.c
cpu_ops_spinwait.c
cpu_ops.c
cpu-hotplug.c
cpu.c
cpufeature.c
entry.S
fpu.S
ftrace.c
head.h
head.S	riscv: Setup exception vector for nommu platform	2020-08-14 16:28:20 -07:00
irq.c
jump_label.c
kgdb.c
Makefile	RISC-V: Remove CLINT related code from timer and arch	2020-08-20 10:58:13 -07:00
mcount-dyn.S
mcount.S
module-sections.c
module.c
module.lds
patch.c
perf_callchain.c
perf_event.c
perf_regs.c
process.c
ptrace.c
reset.c
riscv_ksyms.c
sbi.c	RISC-V: Add mechanism to provide custom IPI operations	2020-08-20 10:55:40 -07:00
setup.c	RISC-V: Remove CLINT related code from timer and arch	2020-08-20 10:58:13 -07:00
signal.c
smp.c	RISC-V: Remove CLINT related code from timer and arch	2020-08-20 10:58:13 -07:00
smpboot.c	RISC-V: Remove CLINT related code from timer and arch	2020-08-20 10:58:13 -07:00
soc.c
stacktrace.c
sys_riscv.c
syscall_table.c
time.c
traps_misaligned.c
traps.c
vdso.c
vmlinux.lds.S